Document
GS81302D06/11/20/38E-500/450/400/350
165-Bump BGA Commercial Temp Industrial Temp
144Mb SigmaQuad-II+ Burst of 4 SRAM
500 MHz–350 MHz 1.8 V VDD
1.8 V or 1.5 V I/O
Features
• 2.5 Clock Latency • Simultaneous Read and Write SigmaQuad™ Interface • JEDEC-standard pinout and package • Dual Double Data Rate interface • Byte Write controls sampled at data-in time • Burst of 4 Read and Write • On-Die Termination (ODT) on Data (D), Byte Write (BW),
and Clock (K, K) intputs • 1.8 V +100/–100 mV core power supply • 1.5 V or 1.8 V HSTL Interface • Pipelined read operation • Fully coherent read and write pipelines • ZQ pin for programmable output drive strength • Data Valid Pin (QVLD) Support • IEEE 1149.1 JTAG-compliant Boundary Scan • 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package • RoHS-compliant 165-bump BGA package available
SigmaQuad™ Family Overview
The GS81302D06/11/20/38E are built in compliance with the SigmaQuad-II+ SRAM pinout standard for Separate I/O synchronous SRAMs. They are 150,994,944-bit (144Mb) SRAMs. The GS81302D06/11/20/38E SigmaQuad SRAMs
are just one element in a family of low power, low voltage HSTL I/O SRAMs designed to operate at the speeds needed to implement economical high performance networking systems.
Clocking and Addressing Schemes
The GS81302D06/11/20/38E SigmaQuad-II+ SRAMs are synchronous devices. They employ two input register clock inputs, K and K. K and K are independent single-ended clock inputs, not differential inputs to a single differential clock input buffer.
Each internal read and write operation in a SigmaQuad-II+ B4 RAM is four times wider than the device I/O bus. An input data bus de-multiplexer is used to accumulate incoming data before it is simultaneously written to the memory array. An output data multiplexer is used to capture the data produced from a single memory array read and then route it to the appropriate output drivers as needed. Therefore the address field of a SigmaQuad-II+ B4 RAM is always two address pins less than the advertised index depth (e.g., the 16M x 8 has a 4M addressable index).
tKHKH tKHQV
Parameter Synopsis
-500 2.0 ns 0.45 ns
-450 2.2 ns 0.45 ns
-400 2.5 ns 0.45 ns
-350 2.86 ns 0.45 ns
Rev: 1.05b 6/2014
1/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology
GS81302D06/11/20/38E-500/450/400/350
4M x 36 SigmaQuad-II+ SRAM—Top View
1 2 3 4 5 6 7 8 9 10 11
A
CQ
NC/SA (288Mb)
SA
W BW2 K BW1 R
SA SA CQ
B Q27 Q18 D18 SA BW3 K BW0 SA D17 Q17 Q8
C D27 Q28 D19 VSS SA NC SA VSS D16 Q7 D8
D D28 D20 Q19 VSS VSS VSS VSS VSS Q16 D15 D7
E
Q29
D29
Q20
VDDQ
VSS
VSS
VSS
VDDQ
Q15
D6
Q6
F
Q30 Q21 D21
VDDQ
VDD
VSS
VDD
VDDQ
D14
Q14
Q5
G
D30 D22 Q22 VDDQ VDD
VSS
VDD
VDDQ
Q13
D13
D5
H
Doff
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
VREF
ZQ
J
D31
Q31
D23
VDDQ
VDD
VSS
VDD
VDDQ
D12
Q4
D4
K
Q32 D32 Q23 VDDQ VDD
VSS
VDD
VDDQ
Q12
D3
Q3
L
Q33
Q24
D24
VDDQ
VSS
VSS
VSS
VDDQ
D11
Q11
Q2
M D33 Q34 D25 VSS VSS VSS VSS VSS D10 Q1 D2
N
D34 D26 Q25 VSS SA
SA
SA
VSS Q10
D9
D1
P
Q35 D35 Q26
SA
SA QVLD SA
SA
Q9
D0
Q0
R
TDO TCK
SA
SA
SA ODT SA
SA
SA TMS TDI
11 x 15 Bump BGA—15 x 17 mm2 Body—1 mm Bump Pitch
Notes: 1. BW0 controls writes to D0:D8; BW1 controls writes to D9:D17; BW2 controls writes to D18:D26; BW3 controls writes to D27:D35 2. Pin A2 is the expansion address.
Rev: 1.05b 6/2014
2/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology
GS81302D06/11/20/38E-500/450/400/350
8M x 18 SigmaQuad-II+ SRAM—Top View
123456789
A
CQ SA SA
W
BW1
K
NC/SA (288Mb)
R
SA
B NC Q9 D9 SA NC K BW0 SA NC
C NC NC D10 VSS SA NC SA VSS NC
D NC D11 Q10 VSS VSS VSS VSS VSS NC
E NC NC Q11 VDDQ VSS VSS VSS VDDQ NC
F
NC
Q12
D12
VDDQ
VDD
VSS
VDD VDDQ NC
G
NC
D13
Q13
VDDQ
VDD
VSS
VDD VDDQ NC
H
Doff
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
J
NC
NC
D14
VDDQ
VDD
VSS
VDD VDDQ NC
K NC NC Q14 VDDQ VDD VSS VDD VDDQ NC
L NC Q15 D15 VDDQ VSS VSS VSS VDDQ NC
M NC NC D16 VSS VSS VSS VSS VSS NC
N NC D17 Q16 VSS SA SA SA VSS NC
P NC NC Q17 SA SA QVLD SA SA NC
R
TDO TCK
SA
SA
SA ODT SA
SA
SA
11 x 15 Bump BGA—15 x 17 mm2 Body—1 mm Bump Pitch
Notes: 1. BW0 controls writes to D0:D8. BW1 controls writes to D9:D17. 2. Pin A7 is the expansion address.
10 SA NC Q7 NC D6 NC NC VREF Q4 D3 NC Q1 NC D0 TMS
11 CQ Q8 D8 D7 Q6 Q5 D5 ZQ D4 Q3 Q2 D2 D1 Q0 TDI
Rev: 1.05b 6/2014
3/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology
GS81302D06/11/20/38E-500/450/400/350
16M x 9 SigmaQuad-II SRAM—Top View
123456789
A CQ SA SA W NC K SA R SA
B
NC
NC
NC
SA
NC/SA (288Mb)
K
BW0 SA
NC
C NC NC NC VSS SA NC SA VSS NC
D NC D5 NC VSS VSS VSS VSS VSS NC
E
NC
NC
Q5
VDDQ
V.