Document
1Gb DDR2 SDRAM
1Gb DDR2 SDRAM
Lead-Free&Halogen-Free (RoHS Compliant)
H5PS1G63KFR-xxC H5PS1G63KFR-xxI H5PS1G63KFR-xxJ H5PS1G63KFR-xxL
* SK Hynix reserves the right to change products or specifications without notice.
Rev. 1.1 / Mar. 2014
1
Revision Details
Rev. 1.0 1.1
History Official Release Typo Correction
Draft Date Oct. 2013 Mar. 2014
Remark Page11
Rev. 1.1 / Mar. 2014
2
Contents
1. Description
1.1 Device Features and Ordering Information 1.1.1 Key Features 1.1.2 Ordering Information 1.1.3 Operating Frequency
1.2 Pin configuration 1.3 Pin Description
2. Maximum DC ratings
2.1 Absolute Maximum DC Ratings 2.2 Operating Temperature Condition
3. AC & DC Operating Conditions
3.1 DC Operating Conditions 3.1.1 Recommended DC Operating Conditions(SSTL_1.8) 3.1.2 ODT DC Electrical Characteristics
3.2 DC & AC Logic Input Levels 3.2.1 Input DC Logic Level 3.2.2 Input AC Logic Level 3.2.3 AC Input Test Conditions 3.2.4 Differential Input AC Logic Level 3.2.5 Differential AC Output Parameters
3.3 Output Buffer Levels 3.3.1 Output AC Test Conditions 3.3.2 Output DC Current Drive 3.3.3 OCD default characteristics
3.4 IDD Specifications & Measurement Conditions 3.5 Input/Output Capacitance
4. AC Timing Specifications
5. Package Dimensions
Rev. 1.1 / Mar. 2014
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1. Description
1.1 Device Features & Ordering Information
1.1.1 Key Features
• VDD = 1.8 +/- 0.1V • VDDQ = 1.8 +/- 0.1V • All inputs and outputs are compatible with SSTL_18 interface • 8 banks • Fully differential clock inputs (CK, /CK) operation • Double data rate interface • Source synchronous-data transaction aligned to bidirectional data strobe (DQS, DQS) • Differential Data Strobe (DQS, DQS) • Data outputs on DQS, DQS edges when read (edged DQ) • Data inputs on DQS centers when write (centered DQ) • On chip DLL align DQ, DQS and DQS transition with CK transition • DM mask write data-in at the both rising and falling edges of the data strobe • All addresses and control inputs except data, data strobes and data masks latched on the rising
edges of the clock • Programmable CAS latency 3, 4, 5,6 and 7 supported • Programmable additive latency 0, 1, 2, 3, 4 and 5 supported • Programmable burst length 4/8 with both nibble sequential and interleave mode • Internal eight bank operations with single pulsed RAS • Auto refresh and self refresh supported • tRAS lockout supported • 8K refresh cycles /64ms • JEDEC standard 84ball FBGA(x16) • Full strength driver option controlled by EMR • On Die Termination supported • Off Chip Driver Impedance Adjustment supported • Self-Refresh High Temperature Entry • Average Refresh Cycle (Tcase 0 oC~ 95 oC)
- 7.8 µs at 0oC ~ 85 oC - 3.9 µs at 85oC ~ 95 oC Commercial Temperature( 0oC ~ 95 oC) Industrial Temperature( -40oC ~ 95 oC)
Rev. 1.1 / Mar. 2014
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Ordering Information
Part No. H5PS1G63KFR-xx*C H5PS1G63KFR-xx*I
H5PS1G63KFR-xx*L
Configuration
64Mx16
Power Consumption
Normal Consumption Normal Consumption Low Power Consumption
(IDD6 Only)
Operation Temp Commercial Industrial Commercial
Package 84 Ball fBGA
H5PS1G63KFR-xx*J
Low Power Consumption (IDD6 Only)
Industrial
Note:
-XX* is the speed bin, refer to the Operating Frequency table for complete part number.
-xxP and xxQ are the low current bin, refer to the IDD specification table. - SK hynix Halogen-free products are compliant to RoHS. SK hynix supports Lead & Halogen free parts for each speed grade with same specification, except Lead free materials. We'll add "R" character after "F" for Lead & Halogen free products
Operating Frequency
Grade E3 C4 Y5 S6 S5 G7
Note:
tCK(ns) 5
3.75 3 2.5 2.5
1.875
CL 3 4 5 6 5 7
tRCD 3 4 5 6 5 7
tRP 3 4 5 6 5 7
Unit Clk Clk Clk Clk Clk Clk
-G7 is a special speed product used in electronic engineering for high speed storage of the working data of a consumer digital electronic device. - x16 product only
Rev. 1.1/ Mar. 2014
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1.2 Pin Configuration & Address Table
64Mx16 DDR2 PIN CONFIGURATION(Top view: see balls through package)
123
789
VDD NC VSS
A
VSSQ
UDQS
VDDQ
DQ14
VSSQ
UDM
B
UDQS
VSSQ
DQ15
VDDQ DQ9 VDDQ C VDDQ DQ8 VDDQ
DQ12
VSSQ
DQ11
D
DQ10
VSSQ
DQ13
VDD NC VSS
E
VSSQ
LDQS
VDDQ
DQ6 VSSQ LDM
F
LDQS
VSSQ
DQ7
VDDQ DQ1 VDDQ G VDDQ DQ0 VDDQ
DQ4 VSSQ DQ3 H DQ2 VSSQ DQ5
VDDL
VREF
VSS
J
VSSDL
CK
VDD
CKE WE
K RAS CK ODT
BA2 BA0 BA1 L CAS CS
A10/AP
A1
M
A2 A0 VDD
VSS A3
A5
N
A6 A4
VDD
A7 A12
A9 NC
P A11 A8 VSS R NC NC
ROW AND COLUMN ADDRESS TABLE
ITEMS
# of Bank Bank Address Auto Precharge Flag Row Address Column Address
Page size
64Mx16
8 BA0, BA1, BA2
A10/AP A0 - A12
A0-A9 2 KB
Rev. 1.1/ Mar. 2014
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1.3 PIN DESCRIPTION
PIN CK, CK
CKE
CS ODT RAS, CAS, WE DM (LDM, UDM) BA0 - BA2
A0 -Amax DQ
DQS, (DQS) (UDQS),(UDQS) (LDQS),(LDQS) (RDQS),(RDQS)
TYPE
DESCRIPTION
Input
Clock: CK and CK are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of CK. Output (read) data is re.