Document
1Gb DDR2 SDRAM
1Gb DDR2 SDRAM
Lead-Free&Halogen-Free (RoHS Compliant)
H5PS1G63KFR-xxC H5PS1G63KFR-xxI H5PS1G63KFR-xxJ H5PS1G63KFR-xxL
* SK Hynix reserves the right to change products or specifications without notice.
Rev. 1.1 / Mar. 2014
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Revision Details
Rev. 1.0 1.1
History Official Release Typo Correction
Draft Date Oct. 2013 Mar. 2014
Remark Page11
Rev. 1.1 / Mar. 2014
2
Contents
1. Description
1.1 Device Features and Ordering Information 1.1.1 Key Features 1.1.2 Ordering Information 1.1.3 Operating Frequency
1.2 Pin configuration 1.3 Pin Description
2. Maximum DC ratings
2.1 Absolute Maximum DC Ratings 2.2 Operating Temperature Condition
3. AC & DC Operating Conditions
3.1 DC Operating Conditions 3.1.1 Recommended DC Operating Conditions(SSTL_1.8) 3.1.2 ODT DC Electrical Characteristics
3.2 DC & AC Logic Input Levels 3.2.1 Input DC Logic Level 3.2.2 Input AC Logic Level 3.2.3 AC Input Test Conditions 3.2.4 Differential Input AC Logic Level 3.2.5 Differential AC Output Parameters
3.3 Output Buffer Levels 3.3.1 Output AC Test Conditions 3.3.2 Output DC Current Drive 3.3.3 OCD default characteristics
3.4 IDD Specifications & Measurement Conditions 3.5 Input/Output Capacitance
4. AC Timing Specifications
5. Package Dimensions
Rev. 1.1 / Mar. 2014
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1. Description
1.1 Device Features & Ordering Information
1.1.1 Key Features
• VDD = 1.8 +/- 0.1V • VDDQ = 1.8 +/- 0.1V • All inputs and outputs are compatible with SSTL_18 interface • 8 banks • Fully differential clock inputs (CK, /CK) operation • Double data rate interface • Source synchronous-data transaction aligned to bidirectional data strobe (DQS, DQS) • Differential Data Strobe (DQS, DQS) • Data outputs on DQS, DQS edges when read (edged DQ) • Data inputs on DQS centers when write (centered DQ) • On chip DLL align DQ, DQS and DQS transition with CK transition • DM mask write data-in at the both rising and falling edges of the data strobe • All addresses and control inputs except data, data strobes and data masks latched on the rising
edges of the clock • Programmable CAS latency 3, 4, 5,6 and 7 supported • Programmable additive latency 0, 1, 2, 3, 4 and 5 supported • Programmable burst length 4/8 with both nibble sequential and interleave mode • Internal eight bank operations with single pulsed RAS • Auto refresh and self refresh supported • tRAS lockout supported • 8K refresh cycles /64ms • JEDEC standard 84ball FBGA(x16) • Full strength driver option controlled by EMR • On Die Termination supported • Off Chip Driver Impedance Adjustment supported • Self-Refresh High Temperature Entry • Average Refresh Cycle (Tcase 0 oC~ 95 oC)
- 7.8 µs at 0oC ~ 85 oC - 3.9 µs at 85oC ~ 95 oC Commercial Temperature( 0oC ~ 95 oC) Industrial Temperature( -40oC ~ 95 oC)
Rev. 1.1 / Mar. 2014
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Ordering Information
Part No. H5PS1G63KFR-xx*C H5PS1G63KFR-xx*I
H5PS1G63KFR-xx*L
Configuration
64Mx16
Power Consumption
Normal Consumption Normal Consumption Low Power Consumption
(IDD6 Only)
Operation Te.