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74LVC2G02 Dataheets PDF



Part Number 74LVC2G02
Manufacturers NXP
Logo NXP
Description Dual 2-input NOR gate
Datasheet 74LVC2G02 Datasheet74LVC2G02 Datasheet (PDF)

74LVC2G02 Dual 2-input NOR gate Rev. 15 — 15 August 2023 Product data sheet 1. General description The 74LVC2G02 is a dual 2-input NOR gate. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disabl.

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74LVC2G02 Dual 2-input NOR gate Rev. 15 — 15 August 2023 Product data sheet 1. General description The 74LVC2G02 is a dual 2-input NOR gate. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down. 2. Features and benefits • Wide supply voltage range from 1.65 V to 5.5 V • 5 V tolerant outputs for interfacing with 5 V logic • Overvoltage tolerant inputs to 5.5 V • High noise immunity • ±24 mA output drive (VCC = 3.0 V) • CMOS low power consumption • IOFF circuitry provides partial Power-down mode operation • Latch-up performance exceeds 250 mA • Direct interface with TTL levels • Complies with JEDEC standard: • JESD8-7 (1.65 V to 1.95 V) • JESD8-5 (2.3 V to 2.7 V) • JESD8-B/JESD36 (2.7 V to 3.6 V) • ESD protection: • HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V • CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V • Multiple package options • Specified from -40 °C to +85 °C and -40 °C to +125 °C Nexperia 74LVC2G02 Dual 2-input NOR gate 3. Ordering information Table 1. Ordering information Type number Package Temperature range 74LVC2G02DP -40 °C to +125 °C Name TSSOP8 74LVC2G02DC -40 °C to +125 °C VSSOP8 74LVC2G02GT -40 °C to +125 °C XSON8 74LVC2G02GF -40 °C to +125 °C XSON8 74LVC2G02GN -40 °C to +125 °C XSON8 74LVC2G02GS -40 °C to +125 °C XSON8 Description Version plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm SOT505-2 plastic very thin shrink small outline package; 8 leads; SOT765-1 body width 2.3 mm plastic extremely thin small outline package; no leads; SOT833-1 8 terminals; body 1 × 1.95 × 0.5 mm extremely thin small outline package; no leads; 8 terminals; body 1.35 × 1 × 0.5 mm SOT1089 extremely thin small outline package; no leads; 8 terminals; body 1.2 × 1.0 × 0.35 mm SOT1116 extremely thin small outline package; no leads; 8 terminals; body 1.35 × 1.0 × 0.35 mm SOT1203 4. Marking Table 2. Marking codes Type number 74LVC2G02DP 74LVC2G02DC 74LVC2G02GT 74LVC2G02GF 74LVC2G02GN 74LVC2G02GS Marking code[1] V02 V02 V02 VB VB VB [1] The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram 1A 1B 1Y 2A 2Y 2B 001aah780 Fig. 1. Logic symbol 1 1 001aah781 Fig. 2. IEC logic symbol B Y A mna105 Fig. 3. Logic diagram (one gate) 74LVC2G02 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 15 — 15 August 2023 © Nexperia B.V. 2023. All rights reserved 2 / 18 Nexperia 6. Pinning information 74LVC2G02 Dual 2-input NOR gate 6.1. Pinning 74LVC2G02 1A 1 8 VCC 1B 2 7 1Y 2Y 3 6 2B GND 4 5 2A Fig. 4. Pin configuration SOT1089 (XSON8) 001aab643 Transparent top view GT package SOT833-1 (XSON8) 1A 1 8 VCC DP package SOT505-2 (TSSOP8) 1A 1 1B 2 2Y 3 GND 4 8 VCC 7 1Y 6 2B 5 2A aaa-036501 DC package SOT765-1 (VSSOP8) 1A 1 1B 2 2Y 3 GND 4 8 VCC 7 1Y 6 2B 5 2A aaa-036500 1B 2 7 1Y 2Y 3 6 2B GND 4 5 2A aaa-036666 Transparent top view GN package SOT1116 (XSON8) 1A 1 8 VCC 1B 2 7 1Y GS package SOT1203 (XSON8) 1A 1 8 VCC 1B 2 7 1Y 2Y 3 6 2B 2Y 3 6 2B GND 4 5 2A aaa-036667 Transparent top view GND 4 5 2A Transparent top view aaa- 036718 74LVC2G02 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 15 — 15 August 2023 © Nexperia B.V. 2023. All rights reserved 3 / 18 Nexperia 74LVC2G02 Dual 2-input NOR gate 6.2. Pin description Table 3. Pin description Symbol Pin 1A, 2A 1, 5 1B, 2B 2, 6 GND 4 1Y, 2Y 7, 3 VCC 8 Description data input data input ground (0 V) data output supply voltage 7. Functional description Table 4. Function table H = HIGH voltage level; L = LOW voltage level; X = don’t care. Input nA nB L L X H H X Output nY H L L 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Max Unit VCC supply voltage VI input voltage VO output voltage IIK IOK IO ICC IGND Tstg Ptot input clamping current output clamping current output current supply current ground current storage temperature total power dissipation Active mode Power-down mode; VCC = 0 V VI < 0 V VO < 0 V or VO > VCC VO = 0 V to VCC Tamb = -40 °C to +125 °C -0.5 [1] -0.5 [1] -0.5 [1] -0.5 -50 - - - -100 -65 [2] - +6.5 V +6.5 V VCC + 0.5 V +6.5 V - mA ±50 mA ±50 mA 100 mA - mA +150 °C 25.


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