Dual 2-input NAND gate
74LVC2G00
Dual 2-input NAND gate
Rev. 12 — 8 April 2013
Product data sheet
1. General description
The 74LVC2G00 provid...
Description
74LVC2G00
Dual 2-input NAND gate
Rev. 12 — 8 April 2013
Product data sheet
1. General description
The 74LVC2G00 provides a 2-input NAND gate function.
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in a mixed 3.3 V and 5 V environment.
This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.
2. Features and benefits
Wide supply voltage range from 1.65 V to 5.5 V 5 V tolerant outputs for interfacing with 5 V logic High noise immunity 24 mA output drive (VCC = 3.0 V) CMOS low power consumption Complies with JEDEC standard:
JESD8-7 (1.65 V to 1.95 V) JESD8-5 (2.3 V to 2.7 V) JESD8-B/JESD36 (2.7 V to 3.6 V) Latch-up performance exceeds 250 mA Direct interface with TTL levels Inputs accept voltages up to 5 V ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V Multiple package options Specified from 40 C to +85 C and 40 C to +125 C
NXP Semiconductors
74LVC2G00
Dual 2-input NAND gate
3. Ordering information
Table 1. Ordering information Type number Package
Temperature range Name 74LVC2G00DP 40 C to +125 C TSSOP8
74LVC2G00DC 40 C to +125 C VSSOP8
74LVC2G00GT 40 C to +125 C XSON8
74LVC2G00GF 40 C to +125 C XSON8
74LVC2G00GD 40 C to +125 C XSON8
74LVC2G00GM 40 C to +125 C XQFN8
74LVC2...
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