Document
NJW4814
Dual H-Bridge Driver with Boost Converter
GENERAL DESCRIPTION The NJW4814 is a dual H-bridge driver with boost converter IC. It can boost the output voltage from Li-ion battery and/or a 5V power
supply and drives a piezo device by two H- bridge drivers. 48ms of internal fixed soft start function of the boost circuit sets a limit
to startup current. The dual H-bridge drivers have independent signal inputs and a fault
output function, therefore the NJW4814 improves controllability from a microcomputer.
The input frequency of H-bridge driver is up to 300kHz.
■ PACKAGE OUTLINE NJW4814MLE
FEATURES Boost Converter Block
H-Bridge Driver Block
Under Voltage Lockout Built-in Thermal Shutdown Standby Function Package Outline
Output Switch Voltage Switching Current PWM Control Operating Voltage Range Oscillation Frequency Range Soft Start Function Over Current Protection Over Voltage Protection
40V max. 1.5A min.
2.7 to 5.5V 380k to 1MHz 48ms typ.
Internal 2 Channel H-Bridge Each Channel Operates Individually Over Current Protection Operating Voltage Range Switching Frequency Output Shut Down Control Fault Indicator Output
300mA typ. 7.0 to 35V 300kHz max.
NJW4814MLE : EQFN24-LE
Ver.2015-04-07
-1-
NJW4814
PIN CONFIGURATION
OUTA1 PGND OUTB1 VDD_HB VOVP OUTB2
18 17 16 15 14 13
SW 19 PGND 20 RADJ 21
FB 22 RT 23 GND 24
12 OUTA2 11 PGND 10 FLT 9 INB2 8 INB1 7 INA2
123456
Exposed PAD on backside connect to GND
INA1 SHDNBb SHDNAb STBYb VDD_SW IN-
< Top View> NJW4814MLE
PIN FUNCTION 1. IN2. VDD_SW 3. STBYb 4. SHDNAb 5. SHDNBb 6. INA1 7. INA2 8. INB1 9. INB2 10. FLT 11. PGND 12. OUTA2
13. OUTA1 14. PGND 15. OUTB1 16. VDD_HB 17. VOVP 18. OUTB2 19. SW 20. PGND 21. RADJ 22. FB 23. RT 24. GND
-2-
Ver.2015-04-07
BLOCK DIAGRAM
NJW4814
STBYb FB INRADJ
RT
FLT
INA1 SHDNAb INA2
INB1 SHDNBb INB2
Standby ON/OFF
UVLO
Vref 1.0V
ERR.AMP
Oscillator
PWM
Buffer
Soft Start
Thermal Shutdown
OVP
OCP
UVLO
High Side Gate Driver
OCP
Control Logic
Control Logic
Low Side Gate Driver
High Side Gate Driver
Control Logic
Control Logic
Low Side Gate Driver
GND
PGND
High Side Gate Driver
Low Side Gate Driver
High Side Gate Driver
Low Side Gate Driver
VDD_SW SW
VOVP VDD_HB OUTA1 OUTA2
OUTB1 OUTB2
Ver.2015-04-07
-3-
NJW4814
ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
MAXIMUM RATINGS
(Ta=25°C) UNIT
Boost Converter Block Supply Voltage SW pin Voltage RADJ pin Voltage IN- pin Voltage STBYb pin Voltage VOVP pin Voltage (*2)
VDD_SW VSW VRADJ VINVSTBYb VOVP
-0.3 to +6 -0.3 to +40 -0.3 to +6 (*1) -0.3 to +6 (*1) -0.3 to +6 (*1) -0.3 to +40
V V V V V V
H-Bridge Driver Block
Supply Voltage
SHDNAb, SHDNBb pin Voltage INA1, INA2, INB1, INB2 pin Voltage
VDD_HB
VSHDNAb VSHDNBb VINA1 , VINA2 VINB1 , VINB2
-0.3 to +40 -0.3 to +6 (*1)
-0.3 to +6 (*1)
V V
V
General
FLT pin Voltage
Power Dissipation
Junction Temperature Range Operating Temperature Range Storage Temperature Range
VFLT
PD
Tj Topr Tstg
-0.3 to +6
910 (*3) 2,100 (*4) -40 to +150 -40 to +85
-40 to +150
V
mW
C C C
(*1): When Supply voltage is less than +6V, the absolute maximum voltage is equal to the Supply voltage.
(*2): VOVP pin should be connected to VDD_HB pin.
(*3): Mounted on glass epoxy board. (101.5×114.5×1.6mm: based on EIA/JEDEC standard, 2Layers FR-4, with Exposed Pad)
(*4): Mounted on glass epoxy board. (101.5×114.5×1.6mm: based on EIA/JEDEC standard, 4Layers FR-4, with Exposed Pad)
(For 4Layers: Applying 99.5×99.5mm inner Cu area and a thermal via hole to a board based on JEDEC standard JESD51-5)
RECOMMENDED OPERATING CONDITIONS
PARAMETER
SYMBOL
MIN.
Boost Converter Block Supply Voltage STBYb pin Voltage Timing Resistor Oscillating Frequency
H-Bridge Driver Block Supply Voltage Output Switch DC Current SHDNAb, SHDNBb pin Voltage IN1A, IN1B, IN2A, IN2B pin Voltage FLT pin Voltage
VDD_SW VSTBYb
RT fOSC
VDD_HB IOM VSHDNAb VSHDNBb VINA1 , VINA2 VINB1 , VINB2 VFLT
2.7 0 68 380
7 0 0
0 0
TYP.
MAX.
UNIT
- 5.5 V
–
VDD_SW
V
100 200 k
700
1,000
kHz
– 35 V 20 – mA
–
VDD_SW
V
–
VDD_SW
V
– 5.5 V
-4-
Ver.2015-04-07
NJW4814
ELECTRICAL CHARACTERISTICS Boost Converter Block
PARAMETER
SYMBOL
(Unless otherwise noted, VDD_SW=VSTBYb=3.7V, RT=100k , Ta=25 C)
TEST CONDITION
MIN.
TYP.
MAX. UNIT
Under Voltage Lockout Block UVLO Release Voltage UVLO Operate Voltage UVLO Hysteresis Voltage
Soft Start Block Soft Start Time
VRUVLO_SW VDUVLO_SW
VUVLO_SW
VRUVLO_SW - VDUVLO_SW
TSS VB=0.95V
Oscillator Block
Oscillation Frequency
Oscillation Frequency deviation (Supply voltage) Oscillation Frequency deviation (Temperature)
fOSC RT=100k fDV VDD_SW=3.0V to 5.5V
fDT Ta= -40 C to +85 C
Error Amplifier Block
Reference Voltage
Input Bias Current
IN- pin Clamp Voltage
RADJ pin FET ON Resistance RADJ pin FET Leak Current
VB IB VCLIN-
RON_RADJ
Short IN- and FB, Measuring IN- Pin VB=1.0V VSTBYb=0V, VDD_SW=5.5V, ICLIN-=10 A
IRADJ=10mA
ILEAK_RADJ VSTBYb=0V, VRADJ=3.3V
PWM Comparate Block Maximum Duty Cycle
Output Block Swi.