Document
Standard Products
UT54ACS240/UT54ACTS240
Octal Buffers & Line Drivers, Inverted Three-State Outputs
Datasheet November 2010 www.aeroflex.com/logic
FEATURES Three-state outputs drive bus lines or buffer memory address
registers 1.2μ CMOS
- Latchup immune High speed Low power consumption Single 5 volt supply Available QML Q or V processes Flexible package
- 20-pin DIP - 20-lead flatpack UT54ACS240 - SMD 5962-96568 UT54ACTS240 - SMD 5962-96569
DESCRIPTION
The UT54ACS240 and the UT54ACTS240 are inverting octal buffer and line drivers which improve the performance and density of three-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters.
The devices are characterized over full military temperature range of -55°C to +125°C.
FUNCTION TABLE
INPUTS
OUTPUT
1G, 2G
A
Y
L LH
LHL
HXZ
PINOUTS
1G 1A1 2Y4 1A2 2Y3 1A3 2Y2 1A4 2Y1 VSS
LOGIC SYMBOL
1G (1) (2)
1A1 (4)
1A2 (6)
1A3 (8)
1A4
EN
(18) 1Y1
(16) 1Y2
(14) 1Y3
(12) 1Y4
(19) 2G
EN
(11) 2A1
(13) 2A2
(15) 2A3 2A4 (17)
(9) 2Y1
(7) 2Y2
(5) 2Y3
(3) 2Y4
Note: 1. Logic symbol in accordance with ANSI/IEEE Std 91-1984 and IEC
Publication 617-12.
1
20-Pin DIP Top View
1G 1 20 VDD 1A1 2 19 2G 2Y4 3 18 1Y1 1A2 4 17 2A4 2Y3 5 16 1Y2 1A3 6 15 2A3 2Y2 7 14 1Y3 1A4 8 13 2A2 2Y1 9 12 1Y4 VSS 10 11 2A1
20-Lead Flatpack Top View
1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11
VDD 2G 1Y1 2A4 1Y2 2A3 1Y3 2A2 1Y4 2A1
LOGIC DIAGRAM
1G (1) 1A1 (2) 1A2 (4)
(6) 1A3 1A4 (8)
(18) 1Y1 (16) 1Y2 (14)
1Y3 (12) 1Y4
2G (19) 2A1 (11) 2A2 (13)
(15) 2A3 2A4 (17)
(9) 2Y1 (7) 2Y2 (5)
2Y3 (3) 2Y4
2
OPERATIONAL ENVIRONMENT1 PARAMETER Total Dose SEU Threshold 2 SEL Threshold Neutron Fluence
LIMIT 1.0E6
80
120 1.0E14
UNITS rads(Si) MeV-cm2/mg MeV-cm2/mg n/cm2
Notes: 1. Logic will not latchup during radiation exposure within the limits defined in the table 2. Device storage elements are immune to SEU affects.
ABSOLUTE MAXIMUM RATINGS
SYMBOL
PARAMETER
LIMIT
UNITS
VDD VI/O TSTG TJ TLS ΘJC
II PD
Supply voltage Voltage any pin Storage Temperature range Maximum junction temperature Lead temperature (soldering 5 seconds) Thermal resistance junction to case DC input current Maximum power dissipation
-0.3 to 7.0 -.3 to VDD +.3
-65 to +150 +175 +300 20 ±10 1
V V °C °C °C °C/W mA W
Note:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device at these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
SYMBOL VDD VIN TC
PARAMETER Supply voltage Input voltage any pin Temperature range
LIMIT 4.5 to 5.5 0 to VDD -55 to + 125
UNITS V V °C
3
DC ELECTRICAL CHARACTERISTICS 7
(VDD = 5.0V ±10%; VSS = 0V 6, -55°C < TC < +125°C); Unless otherwise noted, Tc is per the temperature range ordered.
SYMBOL VIL
VIH
IIN VOL
VOH
IOZ IOS IOL IOH Ptotal
PARAMETER
Low-level input voltage 1 ACTS ACS
High-level input voltage 1 ACTS ACS
Input leakage current ACTS/ACS
Low-level output voltage 3 ACTS ACS
High-level output voltage 3 ACTS ACS
Three-state output leakage current
Short-circuit output current 2 ,4 ACTS/ACS
Output current10 (Sink)
Output current10 (Source)
Power dissipation 2, 8, 9
IDDQ ΔIDDQ
Quiescent Supply Current Quiescent Supply Current Delta
ACTS
CIN COUT
Input capacitance 5 Output capacitance 5
CONDITION
VIN = VDD or VSS
IOL = 12.0mA IOL = 100μA
IOH = -12.0mA IOH = -100μA VO = VDD and VSS
VO = VDD and VSS VIN = VDD or VSS VOL = 0.4V VIN = VDD or VSS VOH = VDD - 0.4V CL = 50pF VDD = 5.5V For input under test VIN = VDD - 2.1V For all other inputs VIN = VDD or VSS VDD = 5.5V ƒ = 1MHz @ 0V ƒ = 1MHz @ 0V
MIN
.5VDD .7VDD
-1
MAX
UNIT
0.8 .3VDD
V
V
1 μA
0.40 V 0.25
.7VDD VDD - 0.25
-30
-300
12
30 300
V μA mA mA
-12 mA
2.1 mW/ MHz
10 μA 1.6 mA
15 pF 15 pF
4
Notes: 1. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: VIH = VIH(min) + 20%, - 0%; VIL = VIL(max) + 0%, -
50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but are guaranteed to VIH(min) and VIL(max). 2. Supplied as a design limit but not guaranteed or tested. 3. Per MIL-PRF-38535, for current density ≤ 5.0E5 amps/cm2, the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765 pF/MHz. 4. Not more than one output may be shorted at a time for maximum duration of one second. 5. Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and VSS at frequency of 1MHz and a signal amplitude of 50mV rms maximum. 6. Maximum allowable relative shift equals 50mV. 7. All specifications valid for radiation dose ≤ 1.