UT54ACTS280

Standard Products UT54ACS280/UT54ACTS280 9-Bit Parity Generators/Checkers Datasheet November 2010 www.aeroflex.com/logic FEATURES ‰ Generates either odd or even parity for nine data lines ‰ Cascadable for n-bits parity ‰ 1.2μ CMOS - Latchup immune ‰ High speed ‰ Low power consumption ‰ Single 5 volt supply ‰ Available QML Q or V processes ‰ Flexible package - 14-pin DIP - 14-lead flatpack ‰ UT54ACS280 - SMD 5962-96582 ‰ UT54ACTS280 - SMD 5962-96583 DESCRIPTION The UT54ACS280 and the UT54ACTS280 are 9-bit parity generators/checkers that use high-performance circuitry and features odd and even outputs to facilitate operation of either odd or even parity application. The word-length capability is easily expanded by cascading. The devices are characterized over full military temperature range of -55°C to +125°C. FUNCTION TABLE NUMBER OF INPUTS A THRU I THAT ARE HIGH 0,2,4,6,8 1,3,5,7,9 OUTPUT Σ EVEN H L Σ ODD L H LOGIC SYMBOL PINOUTS 14-Pin DIP Top View G H NC I ∑ EVEN ∑ ODD VSS 1 14 2 13 3 12 4 11 5 10 69 78 VDD F E D C B A G H NC I ∑ EVEN ∑ ODD VSS 14-Lead Flatpack Top View 1 14 2 13 3 12 4 11 5 10 69 78 (8) A (9) B (10) C (11) D (12) E (13) F (1) G (2) H I (4) 2k (5) ∑ EVEN (6) ∑ ODD Note: 1. Logic symbol in accordance with ANSI/IEEE standard 91-1984 and IEC Publication 617-12. 1 VDD F E D C B A LOGIC DIAGRAM A (8) B (9) C (10) (11) D E (12) F (13) (1) G (2) H (4) I 2 (5) Σ EVEN (6) Σ ODD OPERATIONAL ENVIRONMENT1 PARAMETER Total Dose SEU Threshold 2 SE...