Gen2 / Gen3 Buffer
Features
ÎÎPCIe Gen2/ Gen3* compliant clock buffer/ZDB
* Gen3 performance only available in Commercial temp
ÎÎInternal e...
Description
Features
ÎÎPCIe Gen2/ Gen3* compliant clock buffer/ZDB
* Gen3 performance only available in Commercial temp
ÎÎInternal equalization for better signal integrity ÎÎ2 HCSL outputs ÎÎDual PLL bandwidth for SSC tracking ÎÎCycle-to-Cycle Jitter : 40ps (typ) ÎÎOutput-to-Output Skew <10ps ÎÎ3.3V supply voltage ÎÎTSSOP-20 packages
Applications
ÎÎServers ÎÎEmbedded computing systems ÎÎNetworking systems
Block Diagram
PI6CEQ20200
PCIe® Gen2 / Gen3 Buffer
Description
The PI6CEQ20200 is a high performance PCIe Gen2/ Gen3 zero delay buffer with two HCSL outputs. Pericom’s proprietary equalization technique used in this device improves signal integrity and makes this device suitable for PCIe Gen2/ Gen3 applications even when the input from the main clock has to travel a long distance.
Pin Configuration (20-Pin TSSOP & 20-Pin QSOP)
SRCIN SRCIN#
EQ
PLL_BW_SEL SCLK
SDATA
Control
PLL
OE0#
CLK0 CLK0#
OE1#
CLK1 CLK1#
PLL_BW_SEL SRCIN
SRCIN# OE_0# VDD GND CLK0 CLK0# VDD SDATA
1 2 3 4 5 6 7 8 9 10
20 VDDA 19 GNDA 18 IRef 17 OE_1# 16 VDD 15 GND 14 CLK1 13 CLK1# 12 VDD 11 SCLK
15-0058
1 www.pericom.com
Rev B
05/05/15
Pin Description
Pin #
1 2, 3
Pin Name
PLL_BW_SEL SRCIN, SRCIN#
4 OE_0#
5, 9, 12, 16 6, 15 7, 8 10 11 13, 14
VDD GND CLK0, CLK0# SDATA SCLK CKL1#, CLK1
17 OE_1#
18 IRef 19 GNDA 20 VDDA
PI6CEQ20200 PCIe® Gen2 / Gen3 Buffer with Equalization
Type Input Input
Input
Power Power Input Input/Output Input Output
Input
Input Power Power
Description
CMOS input to sele...
Similar Datasheet