Document
PI6CFGL402B
Low Power PCIe 3.0 Clock Generator with 4 HCSL Outputs
Features
• PCIe® 3.0, 2.0 and 1.0 complaint • LVDS compatible outputs • Supply voltage of 3.3V ±5% • 25MHz crystal or clock input frequency • Low power consumption with independent output power
supply 1.05V to 3.3V • Jitter 40ps cycle-to-cycle (typ) • Spread of -0.5%, -1.0%, -1.5%, and no spread • Industrial temperature range • Spread Bypass option available • Spread and frequency selection via external pins • Packaging: (Pb-free and Green) →20-pin, 173-mil wide TSSOP
Description
The PI6CFGL402B is a spread spectrum clock generator compliant to PCI Express® 3.0 and Ethernet requirements. The device is used for PC or embedded systems to substantially reduce Electromagnetic Interference (EMI). The PI6CFGL402B provides four differential (HCSL) or LVDS spread spectrum outputs. The PI6CFGL402B is configured to select spread and clock selection. Using Pericom's patented Phase-Locked Loop (PLL) techniques, the device takes a 25MHz crystal input and produces four pairs of differential outputs (HCSL) at 100MHz and 200MHz clock frequencies. It also provides spread selection of -0.5%, -1.0%, -1.5%, and no spread.
Block Diagram
VDD PD OE
2
S[2:0] 3
Spread Spectrum/
Output clock selection
SS Circuitry
25 MHzX1/CLK crystal or clock X2
Crystal Driver
PCualpliancgitors
PLL
2
GND
Pin Configuration
CLK0 CLK0 CLK1 CLK1 CLK2 CLK2 CLK3 CLK3
VDDA3.3 S0 S1 S2 X1 X2 PD OE
GNDXD VDDDIG3.3
1 2 3 4 5 6 7 8 9 10
20 CLK0 19 CLK0 18 CLK1 17 CLK1 16 GNDA 15 VDDO 14 CLK2 13 CLK2 12 CLK3 11 CLK3
All trademarks are property of their respective owners.
15-0032
1
www.pericom.com 03/03/15
PI6CFGL402B
Low Power PCIe 3.0 Clock Generator with 4 HCSL Outputs
Pin Description
Pin #
1
2 3 4 5 6 7
Pin Name
VDDA3.3 S0 S1 S2 X1 X2 PD
8 OE
9 GNDXD 10 VDDDIG3.3
11 CLK3
12 CLK3
13 CLK2
14 CLK2
15 VDDO 16 GNDA
17 CLK1
18 CLK1
19 CLK0
20 CLK0
I/O Type Power Input Input Input Input Output Input Input Power Power Output
Output
Output
Output Power Power Output
Output
Output
Output
Description
3.3V power for PLL core. Spread Spectrum Select pin #0. See Spread Selection Table. Internal pull-up resistor. Spread Spectrum Select pin #1. See Spread Selection Table. Internal pull-up resistor. Spread Spectrum Select pin #2. See Spread Selection Table. Internal pull-up resistor. Crystal connection. Crystal connection. Power down. Internal pull-up resistor. Output enable. Tri-states output (High=enable outputs); Low=disable outputs). Internal pullup resister. Connect to digital circuit ground. 3.3V digital power. Selectable 100/200 MHz Spread Spectrum differential compliment output clock 3. LOW when output is disabled. Selectable 100/200 MHz Spread Spectrum differential true output clock 3. LOW when output is disabled. Selectable 100/200 MHz Spread Spectrum differential compliment output clock 2. LOW when output is disabled. Selectable 100/200 MHz Spread Spectrum differential true output clock .