30N50Q

HiPerFETTM Power MOSFETs ISOPLUS247TM IXFR 30N50Q (Electrically Isolated Back Surface) IXFR 32N50Q N-Channel Enhancement Mode High dV/dt, Low trr, HDMOSTM Family VDSS ID25 500 V 29 A 500 V 30 A trr £ 250 ns RDS(on) 0.16 W 0.15 W Preliminary data Symbol VDSS VDGR VGS VGSM ID25 I DM I AR EAS EAR dv/dt PD TJ TJM Tstg TL VISOL Weight Test Conditions Maximum Ratings TJ = 25°C to 150°C TJ = 25°C to 150°C; RGS = 1 MW Continuous Transient 500 500 ±20 ±30 TC = 25°C T C = 25°C, Pulse width limited by T JM T C = 25°C TC = 25°C TC = 25°C IS £ IDM, di/dt £ 100 A/ms, VDD £ VDSS TJ £ 150°C, RG = 2 W TC = 25°C 30N50 32N50 30N50 32N50 30N50 32N50 30 120 30 1.5 45 5 310 -55 ... +150 150 -55 ... +150 1.6 mm (0.062 in.) from case for 10 s 300 50/60 Hz, RMS t = 1 minute leads-to-tab 2500 6 V V V V A A A J mJ V/ns W °C °C °C °C V~ g ISOPLUS 247TM E 153432 G D Isolated back surface* G = Gate S = Source D = Drain * Patent pending Features Silicon chip on Direct-Copper-Bond substrate - High power dissipation - Isolated mounting surface - 2500V electrical isolation Low drain to tab capacitance(<50pF) Low RDS (on) HDMOSTM process Rugged polysilicon gate cell structure Unclamped Inductive Switching (UIS) rated Fast intrinsic Rectifier Symbol Test Conditions VDSS V GS(th) IGSS IDSS RDS(on) VGS = 0 V, ID = 1mA V = V , I = 4mA DS GS D VGS = ±20 VDC, VDS = 0 VDS = VDSS VGS = 0 V VGS = 10 V, ID = IT Notes 1, 2 Characteristic Values (TJ = 25°C, unles...