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74F676 Dataheets PDF



Part Number 74F676
Manufacturers National Semiconductor
Logo National Semiconductor
Description 16-Bit Serial/Parallel-In / Serial-Out Shift Register
Datasheet 74F676 Datasheet74F676 Datasheet (PDF)

54F 74F676 16-Bit Serial Parallel-In Serial-Out Shift Register December 1994 54F 74F676 16-Bit Serial Parallel-In Serial-Out Shift Register General Description The ’F676 contains 16 flip-flops with provision for synchronous parallel or serial entry and serial output When the Mode (M) input is HIGH information present on the parallel data (P0 – P15) inputs is entered on the falling edge of the Clock Pulse (CP) input signal When M is LOW data is shifted out of the most significant bit position .

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54F 74F676 16-Bit Serial Parallel-In Serial-Out Shift Register December 1994 54F 74F676 16-Bit Serial Parallel-In Serial-Out Shift Register General Description The ’F676 contains 16 flip-flops with provision for synchronous parallel or serial entry and serial output When the Mode (M) input is HIGH information present on the parallel data (P0 – P15) inputs is entered on the falling edge of the Clock Pulse (CP) input signal When M is LOW data is shifted out of the most significant bit position while information present on the Serial (SI) input shifts into the least significant bit position A HIGH signal on the Chip Select (CS) input prevents both parallel and serial operations Features Y 16-bit parallel-to-serial conversion Y 16-bit serial-in serial-out Y Chip select control Y Slim 24 lead 300 mil package Commercial 74F676PC 74F676SPC 74F676SC (Note 1) Military 54F676DM (Note 2) 54F676SDM (Note 2) 54F676FM (Note 2) 54F676LM (Note 2) Package Number N24A N24C J24A J24F M24B W24C E28A Package Description 24-Lead (0 600 Wide) Molded Dual-In-Line 24-Lead (0 300 Wide) Molded Dual-In-Line 24-Lead (0 600 Wide) Ceramic Dual-In-Line 24-Lead (0 300 Wide) Ceramic Dual-In-Line 24-Lead (0 300 Wide) Molded Small Outline JEDEC 24-Lead Cerpack 24-Lead Ceramic Leadless Chip Carrier Type C Note 1 Devices also available in 13 reel Use suffix e SCX Note 2 Military grade device with environmental and burn-in processing Use suffix e DMQB FMQB and LMQB Connection Diagrams Pin Assignment for DIP SOIC and Flatpak Pin Assignment for LCC TL F 9588 – 2 TRI-STATE is a registered trademark of National Semiconductor Corporation C1995 National Semiconductor Corporation TL F 9588 TL F 9588 – 3 RRD-B30M105 Printed in U S A Logic Symbols IEEE IEC TL F 9588 – 1 Unit Loading Fan Out Pin Names P0 – P15 CS CP M SI SO Description Parallel Data Inputs Chip Select Input (Active LOW) Clock Pulse Input (Active LOW) Mode Select Input Serial Data Input Serial Output 54F 74F UL HIGH LOW 10 10 10 10 10 10 10 10 10 10 50 33 3 Input IIH IIL Output IOH IOL 20 mA b0 6 mA 20 mA b0 6 mA 20 mA b0 6 mA 20 mA b0 6 mA 20 mA b0 6 mA b1 mA 20 mA TL F 9588 – 4 Functional Description The 16-bit shift register operates in one of three modes as indicated in the Shift Register Operations Table HOLD a HIGH signal on the Chip Select (CS) input prevents clocking and data is stored in the sixteen registers Shift Serial Load data present on the SI pin shifts into the register on the falling edge of CP Data enters the Q0 position and shifts toward Q15 on successive clocks finally appearing on the SO pin Parallel Load data present on P0 – P15 are entered into the register on the falling edge of CP The SO output represents the Q15 register output To prevent false clocking CP must be LOW during a LOWto-HIGH transition of CS Block Diagram Shift Register Operations Table Control Input CS M CP HX X L LK L HK H e HIGH Voltage Level L e LOW Voltage Level X e Immaterial K e HIGH-to-LOW Transition Operating Mode Hold Shift Serial Load Parallel Load TL F 9588 – 5 2 Absolute Maximum Ratings (Note 1) If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Storage Temperature b65 C to a150 C Ambient Temperature under Bias b55 C to a125 C Junction Temperature under Bias Plastic b55 C to a175 C b55 C to a150 C VCC Pin Potential to Ground Pin b0 5V to a7 0V Input Voltage (Note 2) b0 5V to a7 0V Input Current (Note 2) b30 mA to a5 0 mA Voltage Applied to Output in HIGH State (with VCC e 0V) Standard Output TRI-STATE Output b0 5V to VCC b0 5V to a5 5V Current Applied to Output in LOW State (Max) twice the rated IOL (mA) Note 1 Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired Functional operation under these conditions is not implied Note 2 Either voltage limit or current limit is sufficient to protect inputs Recommended Operating Conditions Free Air Ambient Temperature Military Commercial b55 C to a125 C 0 C to a70 C Supply Voltage Military Commercial a4 5V to a5 5V a4 5V to a5 5V DC Electrical Characteristics Symbol Parameter 54F 74F Min Typ Max Units VCC Conditions VIH VIL VCD VOH VOL IIH Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Current 54F 10% VCC 74F 10% VCC 74F 5% VCC 54F 10% VCC 74F 10% VCC 54F 74F 20 25 25 27 V Recognized as a HIGH Signal 08 V Recognized as a LOW Signal b1 2 V Min IIN e b18 mA IOH e b1 mA V Min IOH e b1 mA IOH e b1 mA 0 5 V Min IOL e 20 mA 0 5 IOL e 20 mA 20 0 50 mA Max VIN e 2 7V IBVI Input HIGH Current 54F Breakdown Test 74F 100 mA Max VIN e 7 0V 70 ICEX Output HIGH Leakage Current 54F 74F 250 mA Max VOUT e VCC 50 VID Input Leakage 74F Test 4 75 V 0 0 IID e 1 9 mA All Other Pins Grounded IOD Output Leakage 74F Circuit Current 3 75 mA 0 0 VIOD e 1.


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