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IS45S16320F Dataheets PDF



Part Number IS45S16320F
Manufacturers ISSI
Logo ISSI
Description 512Mb SDRAM
Datasheet IS45S16320F DatasheetIS45S16320F Datasheet (PDF)

IS42R86400F/16320F, IS45R86400F/16320F IS42S86400F/16320F, IS45S86400F/16320F 32Mx16, 64Mx8 512Mb SDRAM FEATURES • Clock frequency: 200, 166, 143 MHz • Fully synchronous; all signals referenced to a positive clock edge • Internal bank for hiding row access/precharge • Power supply: Vdd/Vddq = 2.3V-3.6V IS42/45SxxxxxF - Vdd/Vddq = 3.3V IS42/45RxxxxxF - Vdd/Vddq = 2.5 • LVTTL interface • Programmable burst length – (1, 2, 4, 8, full page) • Programmable burst sequence: Sequential/Interleave • Aut.

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IS42R86400F/16320F, IS45R86400F/16320F IS42S86400F/16320F, IS45S86400F/16320F 32Mx16, 64Mx8 512Mb SDRAM FEATURES • Clock frequency: 200, 166, 143 MHz • Fully synchronous; all signals referenced to a positive clock edge • Internal bank for hiding row access/precharge • Power supply: Vdd/Vddq = 2.3V-3.6V IS42/45SxxxxxF - Vdd/Vddq = 3.3V IS42/45RxxxxxF - Vdd/Vddq = 2.5 • LVTTL interface • Programmable burst length – (1, 2, 4, 8, full page) • Programmable burst sequence: Sequential/Interleave • Auto Refresh (CBR) • Self Refresh • 8K refresh cycles every 64 ms • Random column address every clock cycle • Programmable CAS latency (2, 3 clocks) • Burst read/write and burst read/single write operations capability • Burst termination by burst stop and precharge command • Packages: x8/x16: 54-pin TSOP-II, 54-ball TF-BGA (x16 only) • Temperature Range: Commercial (0oC to +70oC) Industrial (-40oC to +85oC) Automotive, A1 (-40oC to +85oC) Automotive, A2 (-40oC to +105oC) JULY 2017 device OVERVIEW ISSI's 512Mb Synchronous DRAM achieves high-speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input. The 512Mb SDRAM is organized as follows. PACKAGE INFORMATION IS42/45S16320F IS42/45S86400F IS42/45R16320F IS42/45R86400F 8M x 16 x 4 banks 16M x 8 x 4 banks 54-pin TSOP-II 54-pin TSOP-II 54-ball TF-BGA KEY TIMING PARAMETERS Parameter Clk Cycle Time CAS Latency = 3 CAS Latency = 2 Clk Frequency CAS Latency = 3 CAS Latency = 2 Access Time from Clock CAS Latency = 3 CAS Latency = 2 -5 -6 5 6 10 10 200 167 100 100 5 5.4 6 6 -7 Unit 7 ns 7.5 ns 143 Mhz 133 Mhz 5.4 ns 5.4 ns ADDRESS TABLE Parameter Configuration Bank Address Pins/Balls Autoprecharge Pins/Ball Row Address Column Address Refresh Count Com./Ind./A1 A2 32M x 16 8M x 16 x 4 banks BA0, BA1 A10/AP 8K(A0 – A12) 1K(A0 – A9) 8K / 64ms 8K / 16ms 64M x 8 16M x 8 x 4 banks BA0, BA1 A10/AP 8K(A0 – A12) 2K(A0 – A9, A11) 8K / 64ms 8K / 16ms Copyright © 2017 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized; b.) the user assume all such risks; and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc. — www.issi.com 1 Rev. B1 07/17/2017 IS42/45R86400F/16320F IS42/45S86400F/16320F DEVICE OVERVIEW The 512Mb SDRAM is a high speed CMOS, dynamic random-access memory designed to operate in either 3.3V Vdd/Vddq or 2.5V Vdd/Vddq memory systems, depending on the DRAM option. Internally configured as a quad-bank DRAM with a synchronous interface. The 512Mb SDRAM (536,870,912 bits) includes an AUTO REFRESH MODE, and a power-saving, power-down mode. All signals are registered on the positive edge of the clock signal, CLK. All inputs and outputs are LVTTL compatible. The 512Mb SDRAM has the ability to synchronously burst data at a high data rate with automatic column-address generation, the ability to interleave between internal banks to hide precharge time and the capability to randomly change column addresses on each clock cycle during burst access. A self-timed row precharge initiated at the end of the burst sequence is available with the AUTO PRECHARGE function enabled.  Precharge one bank while accessing one of the other three banks will hide the precharge cycles and provide seamless, high-speed, random-access operation. SDRAM read and write accesses are burst oriented starting at a selected location and continuing for a programmed number of locations in a programmed sequence. The registration of an ACTIVE command begins accesses, followed by a READ or WRITE command. The ACTIVE command in conjunction with address bits registered are used to select the bank and row to be accessed (BA0, BA1 select the bank; A0-A12 select the row). The READ or WRITE commands in conjunction with address bits registered are used to select the starting column location for the burst access. Programmable READ or WRITE burst lengths consist of 1, 2, 4 and 8 locations or full page, with a burst terminate op.


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