8Mx32 256Mb DDR2 DRAM
IS43DR32800A, IS43/46DR32801A
8Mx32 256Mb DDR2 DRAM
PRELIMINARY INFORMATION SEPTEMBER 2010
FEATURES • Vdd = 1...
Description
IS43DR32800A, IS43/46DR32801A
8Mx32 256Mb DDR2 DRAM
PRELIMINARY INFORMATION SEPTEMBER 2010
FEATURES Vdd = 1.8V ±0.1V, Vddq = 1.8V ±0.1V
JEDEC standard 1.8V I/O (SSTL_18-compatible)
Double data rate interface: two data transfers per clock cycle
Differential data strobe (DQS, DQS)
4-bit prefetch architecture
On chip DLL to align DQ and DQS transitions with CK
4 internal banks for concurrent operation
Programmable CAS latency (CL) 3, 4, 5, and 6 supported
Posted CAS and programmable additive latency (AL) 0, 1, 2, 3, 4, and 5 supported
WRITE latency = READ latency - 1 tCK
Programmable burst lengths: 4 or 8
Adjustable data-output drive strength, full and reduced strength options
On-die termination (ODT)
DESCRIPTION
ISSI's 256Mb DDR2 SDRAM uses a double-data-rate architecture to achieve high-speed operation. The double-data rate architecture is essentially a 4n-prefetch architecture, with an interface designed to transfer two data words per clock cycle at the I/O balls.
The 256Mb DDR2 SDRAM is provided in a wide bus x32 format, designed to offer a smaller footprint and support compact designs.
ADDRESS TABLE
Parameter
Configuration Refresh Count Row Addressing Column Addressing Bank Addressing Precharge Addressing
8M x 32 Standard Page Size Option 2M x 32 x 4 banks 4K/64ms A0-A11 A0-A8
BA0, BA1 A10/AP
8M x 32 Reduced Page Size Option 2M x 32 x 4 banks 8K/64ms A0-A12 A0-A7
BA0, BA1 A10/AP
OPTIONS Configuration:
8M x 32 (I...
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