IS42S32800

IS42S32800 2M Words x 32 Bits x 4 Banks (256-Mbit) Synchronous DRAM P JANUARY 2008 FEATURES Concurrent auto precharge Clock rate:166/143 MHz Fully synchronous operation Internal pipelined architecture Four internal banks (2M x 32bit x 4bank) Programmable Mode CAS# Latency: 2 or 3 Burst Length:1,2,4,8,or full page Burst Type: interleaved or linear burst Burst-Read-Single-Write Burst stop function Individual byte controlled by DQM0-3 Auto Refresh and Self Refresh 4096 refresh cycles/64ms (15.6µs/row) Single +3.3V ±0.3V power supply Interface:LVTTL Package: 86 Pin TSOP-2,0.50mm Pin Pitch 8x13mm, 90 Ball BGA, Ball pitch 0.8mm Pb-free package is available Power Down and Deep Power Down Mode Partial Array Self Refresh Temperature Compensated Self Refresh Output Driver Strength Selection Please contact Product Manager for Mobile function detail DESCRIPTION The ISSI IS42S32800 is a high-speed CMOS configured as a quad 2M x 32 DRAM with asynchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the 2M x 32 bit banks is organized as 4096 rows by 512 columns by 32 bits. Read and write accesses start at a selected locations in a programmed sequence. Accesses begin with the registration of a BankActive command which is then followed by a Read or Write command. The ISSI IS42S32800 provides for programmable Read or Write burst lengths of 1,2,4,8,or full page, ...