IS45S16100F

IS42/45S16100F, IS42VS16100F 512K Words x 16 Bits x 2 Banks 16Mb SDRAM JUNE 2012 FEATURES Clock frequency: IS42/45S16100F: 200, 166, 143 MHz IS42VS16100F: 133, 100 MHz Fully synchronous; all signals referenced to a positive clock edge Two banks can be operated simultaneously and independently Dual internal bank controlled by A11 (bank select) Single power supply: IS42/45S16100F: Vdd/Vddq = 3.3V IS42VS16100F: Vdd/Vddq = 1.8V LVTTL interface Programmable burst length – (1, 2, 4, 8, full page) Programmable burst sequence: Sequential/Interleave 2048 refresh cycles every 32 ms Random column address every clock cycle Programmable CAS latency (2, 3 clocks) Burst read/write and burst read/single write operations capability Burst termination by burst stop and precharge command Byte controlled by LDQM and UDQM Packages 400-mil 50-pin TSOP-II and 60-ball BGA Lead-free package option Available in Industrial Temperature DESCRIPTION ISSI’s 16Mb Synchronous DRAM IS42S16100F, IS45S16100F and IS42VS16100F are each organized as a 524,288-word x 16-bit x 2-bank for improved performance. The synchronous DRAMs achieve highspeed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input. ADDRESS TABLE Parameter Power Supply Vdd/Vddq Refresh Count Row Addressing IS42/45S16100F IS42VS16100F 3.3V 1.8V 2K/32ms 2K/32ms A0-A10 Column Addressing Bank Addressing Prech...