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IS61DDPB42M18B Dataheets PDF



Part Number IS61DDPB42M18B
Manufacturers Integrated Silicon Solution
Logo Integrated Silicon Solution
Description 36Mb DDR-IIP(Burst 4) CIO SYNCHRONOUS SRAM
Datasheet IS61DDPB42M18B DatasheetIS61DDPB42M18B Datasheet (PDF)

IS61DDPB42M18B/B1/B2 IS61DDPB41M36B/B1/B2 2Mx18, 1Mx36 36Mb DDR-IIP(Burst 4) CIO SYNCHRONOUS SRAM (2.5 Cycle Read Latency) NOVEMBER 2014 FEATURES DESCRIPTION  1Mx36 and 2Mx18 configuration available.  On-chip Delay-Locked Loop (DLL) for wide data valid window.  Common I/O read and write ports.  Synchronous pipeline read with self-timed late write operation.  Double Data Rate (DDR) interface for read and write input ports.  2.5 cycle read latency.  Fixed 4-bit burst for read and write .

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IS61DDPB42M18B/B1/B2 IS61DDPB41M36B/B1/B2 2Mx18, 1Mx36 36Mb DDR-IIP(Burst 4) CIO SYNCHRONOUS SRAM (2.5 Cycle Read Latency) NOVEMBER 2014 FEATURES DESCRIPTION  1Mx36 and 2Mx18 configuration available.  On-chip Delay-Locked Loop (DLL) for wide data valid window.  Common I/O read and write ports.  Synchronous pipeline read with self-timed late write operation.  Double Data Rate (DDR) interface for read and write input ports.  2.5 cycle read latency.  Fixed 4-bit burst for read and write operations.  Clock stop support.  Two input clocks (K and K#) for address and control registering at rising edges only.  Two echo clocks (CQ and CQ#) that are delivered simultaneously with data.  +1.8V core power supply and 1.5V to 1.8V VDDQ, used with 0.75 to 0.9V VREF.  HSTL input and output interface.  Registered addresses, write and read controls, byte writes, data in, and data outputs.  Full data coherency.  Boundary scan using limited set of JTAG 1149.1 functions.  Byte write capability.  Fine ball grid array (FBGA) package: 13mm x 15mm & 15mm x 17mm body size 165-ball (11 x 15) array  Programmable impedance output drivers via 5x user-supplied precision resistor.  Data Valid Pin (QVLD).  ODT (On Die Termination) feature is supported optionally on data inputs, K/K#, and BWx#.  The end of top mark (B/B1/B2) is to define options. IS61DDPB41M36B : Don’t care ODT function and pin connection IS61DDPB41M36B1 : Option1 IS61DDPB41M36B2 : Option2 Refer to more detail description at page 6 for each ODT option. The 36Mb IS61DDPB41M36B/B1/B2 and IS61DDPB42M18B/B1/B2 are synchronous, highperformance CMOS static random access memory (SRAM) devices. These SRAMs have a common I/O bus. The rising edge of K clock initiates the read/write operation, and all internal operations are self-timed. Refer to the Timing Reference Diagram for Truth Table for a description of the basic operations of these DDR-IIP (Burst of 4) CIO SRAMs. Read and write addresses are registered on alternating rising edges of the K clock. Reads and writes are performed in double data rate. The following are registered internally on the rising edge of the K clock:  Read/write address  Read enable  Write enable  Byte writes  Data-in for first and third burst addresses  Data-out for second and fourth burst addresses The following are registered on the rising edge of the K# clock:  Byte writes  Data-in for second and fourth burst addresses  Data-out for first and third burst addresses Byte writes can change with the corresponding data-in to enable or disable writes on a per-byte basis. An internal write buffer enables the data-ins to be registered one cycle after the write address. The first data-in burst is clocked one cycle later than the write command signal, and the second burst is timed to the following rising edge of the K# clock. Two full clock cycles are required to complete a write operation. During the burst read operation, the data-outs from the first bursts are updated from output registers of the third rising edge of the K# clock (starting two and half cycles later after read command). The data-outs from the second burst are updated with the fourth rising edge of the K clock where read command receives at the first rising edge of K. The device is operated with a single +1.8V power supply and is compatible with HSTL I/O interfaces. Copyright © 2010 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized; b.) the user assume all such risks; and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc.- www.issi.com Rev. A 9/25/2014 1 IS61DDPB42M18B/B1/B2 IS61DDPB41M36B/B1/B2 Package ballout and description x36 FBGA Ball Configuration (Top View) 1234 A CQ# NC/SA1 SA R/W# B NC DQ27 DQ18 SA C NC NC DQ28 VSS D NC DQ29 DQ19 VSS E NC NC DQ20 VDDQ F NC DQ30 DQ21 VDDQ G NC DQ31 DQ22 VDDQ H Doff# VREF VDDQ VDDQ J NC NC DQ32 VDDQ K NC NC DQ23 VDDQ L NC DQ33 DQ24 VDDQ M NC NC DQ34 VSS N NC DQ35 DQ25 VSS P NC NC DQ26 SA R TDO TCK SA SA 5 BW2# BW3# S.


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