72 Mb (2M x 36 & 4M x 18) DDR-IIP (Burs. t of 2) CIO Synchronous SRAMs
(2.5 Cycle Read Latency)
Advanced Information May 2009
Features
2M x 36 or 4M x 18.
On-chip delay-locked loop (DLL) for wide data valid window.
Common data input/output bus. Synchronous pipeline read with self-timed late
write operation.
Double data rate (DDR-IIP) interface f...
