DatasheetsPDF.com

IS61DDP2B22M18A1 Dataheets PDF



Part Number IS61DDP2B22M18A1
Manufacturers Integrated Silicon Solution
Logo Integrated Silicon Solution
Description 36Mb DDR-IIP (Burst 2) CIO SYNCHRONOUS SRAM
Datasheet IS61DDP2B22M18A1 DatasheetIS61DDP2B22M18A1 Datasheet (PDF)

IS61DDP2B22M18A/A1/A2 IS61DDP2B21M36A/A1/A2 2Mx18, 1Mx36 36Mb DDR-IIP (Burst 2) CIO SYNCHRONOUS SRAM (2.0 Cycle Read Latency) ADVANCED INFORMATION JULY 2012 FEATURES DESCRIPTION  1Mx36 and 2Mx18 configuration available.  On-chip Delay-Locked Loop (DLL) for wide data valid window.  Common I/O read and write ports.  Synchronous pipeline read with self-timed late write operation.  Double Data Rate (DDR) interface for read and write input ports.  2.0 cycle read latency.  Fixed 2-bit burst.

  IS61DDP2B22M18A1   IS61DDP2B22M18A1



Document
IS61DDP2B22M18A/A1/A2 IS61DDP2B21M36A/A1/A2 2Mx18, 1Mx36 36Mb DDR-IIP (Burst 2) CIO SYNCHRONOUS SRAM (2.0 Cycle Read Latency) ADVANCED INFORMATION JULY 2012 FEATURES DESCRIPTION  1Mx36 and 2Mx18 configuration available.  On-chip Delay-Locked Loop (DLL) for wide data valid window.  Common I/O read and write ports.  Synchronous pipeline read with self-timed late write operation.  Double Data Rate (DDR) interface for read and write input ports.  2.0 cycle read latency.  Fixed 2-bit burst for read and write operations.  Clock stop support.  Two input clocks (K and K#) for address and control registering at rising edges only.  Two echo clocks (CQ and CQ#) that are delivered simultaneously with data.  +1.8V core power supply and 1.5, 1.8V VDDQ, used with 0.75, 0.9V VREF.  HSTL input and output interface.  Registered addresses, write and read controls, byte writes, data in, and data outputs.  Full data coherency.  Boundary scan using limited set of JTAG 1149.1 functions.  Byte write capability.  Fine ball grid array (FBGA) package: 13mmx15mm and 15mmx17mm body size 165-ball (11 x 15) array  Programmable impedance output drivers via 5x user-supplied precision resistor.  Data Valid Pin (QVLD).  ODT (On Die Termination) feature is supported optionally on data input, K/K#, and BWx#.  The end of top mark (A/A1/A2) is to define options. IS61DDP2B21M36A : Don’t Care ODT function and pin connection IS61DDP2B21M36A1 : Option1 IS61DDP2B21M36A2 : Option2 Refer to more detail description at page 6 for each ODT option. The 36Mb IS61DDP2B21M36A/A1/A2 and IS61DDP2B22M18A/A1/A2 are synchronous, highperformance CMOS static random access memory (SRAM) devices. These SRAMs have a common I/O bus. The rising edge of K clock initiates the read/write operation, and all internal operations are self-timed. Refer to the Timing Reference Diagram for Truth Table for a description of the basic operations of these DDR-IIP (Burst of 2) CIO SRAMs. Read and write addresses are registered on alternating rising edges of the K clock. Reads and writes are performed in double data rate. The following are registered internally on the rising edge of the K clock:  Read/write address  Read enable  Write enable  Byte writes  Data-in for first burst address  Data-Out for first burst address The following are registered on the rising edge of the K# clock:  Byte writes  Data-in for second burst address  Data-Out for second burst address Byte writes can change with the corresponding data-in to enable or disable writes on a per-byte basis. An internal write buffer enables the data-ins to be registered one cycle after the write address. The first data-in burst is clocked one cycle later than the write command signal, and the second burst is timed to the following rising edge of the K# clock. During the burst read operation, the data-outs from the first bursts are updated from output registers of the third rising edge of the K clock (starting two clock cycles later af.


IS61DDP2B22M18A IS61DDP2B22M18A1 IS61DDP2B22M18A2


@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site.
(Privacy Policy & Contact)