I7D7D2DMR-bII
(2M x 36 & 4M x (Burst o. f 4) CIO
18) Synchronous
SRAMs
A MAY 2009
Features
2M x 36 or 4M x 18.
On-chip delay-locked loop (DLL) for wide data valid window.
Common I/O read and write ports.
Synchronous pipeline read with late write operation.
Double data rate (DDR-II) interface for read and write input ports.
Fixed 4-bit burst ...
