IS61DDB42M18A IS61DDB41M36A
2Mx18, 1Mx36 36Mb DDR-II (Burst 4) CIO SYNCHRONOUS SRAM
JANUARY 2015
FEATURES
DESCRIPTION
1Mx36 and 2Mx18 configuration available. On-chip delay-locked loop (DLL) for wide data valid
window.
Common I/O read and write ports. Synchronous pipeline read with late write operation. Double Data Rate (DDR) interface for read...
