72 Mb (2M x 36 & 4M x 18) .
DDR-II (Burst of 2) CIO Synchronous SRAMs
November 2009
Features
2M x 36 or 4M x 18.
On-chip delay-locked loop (DLL) for wide data valid window.
Common data input/output bus.
Synchronous pipeline read with self-timed late write operation.
Double data rate (DDR-II) interface for read and write input ports.
Fixed 2-bit...
