IS61NVVF204836B

IS61NLF204836B/IS61NVF/NVVF204836B IS61NLF409618B/IS61NVF/NVVF409618B  2M x 36 and 4M x 18 72Mb, FLOW THROUGH 'NO WAIT' STATE BUS SRAM ADVANCED INFORMATION FEBRUARY 2013 FEATURES 100 percent bus utilization No wait cycles between Read and Write Internal self-timed write cycle Individual Byte Write Control Single Read/Write control pin Clock controlled, registered address, data and control Interleaved or linear burst sequence control us- ing MODE input Three chip enables for simple depth expansion and address pipelining Power Down mode Common data inputs and data outputs CKE pin to enable clock and suspend operation JEDEC 100-pin TQFP, 119-ball PBGA, and 165- ball PBGA packages Power supply: NLF: Vdd 3.3V (± 5%), Vddq 3.3V/2.5V (± 5%) NVF: Vdd 2.5V (± 5%), Vddq 2.5V (± 5%) NVVF: Vdd 1.8V (± 5%), Vddq 1.8V (± 5%) JTAG Boundary Scan for PBGA packages Industrial temperature available Lead-free available DESCRIPTION The 72 Meg product family features high-speed, low-power synchronous static RAMs designed to provide a burstable, high-performance, 'no wait' state, device for networking and communications applications. They are organized as 2,096,952 words by 36 bits and 4,193,904 words by 18 bits, fabricated with ISSI's advanced CMOS technology. Incorporating a 'no wait' state feature, wait cycles are eliminated when the bus switches from read to write, or write to read. This device integrates a 2-bit burst counter, high-speed S...