IS42VS16160D

IS42VS83200D, IS42VS16160D IS45VS83200D, IS45VS16160D 32Meg x 8, 16Meg x16 PRELIMINARY INFORMATION 256-MBIT SYNCHRONOUS DRAM MAY 2009 FEATURES Clock frequency: 133, 125 MHz Fully synchronous; all signals referenced to a positive clock edge Internal bank for hiding row access/precharge Single Power supply: 1.8V + 0.1V LVCMOS interface Programmable burst length – (1, 2, 4, 8, full page) Programmable burst sequence: Sequential/Interleave Auto Refresh (CBR) Self Refresh 8K refresh cycles every 16 ms (A2 grade) or 8K refresh cycles every 64 ms (Commercial, Industrial, A1 grade) Random column address every clock cycle Programmable CAS latency (2, 3 clocks) Burst read/write and burst read/single write operations capability Burst termination by burst stop and precharge command OPTIONS Package: 54-pin TSOP-II (x8 and x16) 54-ball TF-BGA (x16 only) Operating Temperature Range: Commercial (0oC to +70oC) Industrial (-40oC to +85oC) Automotive Grade, A1 (-40oC to +85oC) Automotive Grade, A2 (-40oC to +105oC) Die Revision: D OVERVIEW ISSI's 256Mb Synchronous DRAM achieves high-speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input. The 256Mb SDRAM is organized as follows. IS42VS83200D IS42VS16160D IS45VS83200D IS45VS16160D 8M x 8 x 4 Banks 4M x16x4 Banks 54-pin TSOPII 54-pin TSOPII 54-ball TF-BGA KEY TIMING PARAMETERS Parameter Clk Cycle Tim...