Document
PT7A7511-15/7521-25/7531-35
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μP Supervisor Circuits
Features
Precision supply-voltage monitor - 4.63V (PT7A7511, 7521, 7531) - 4.38V (PT7A7512, 7522, 7532) - 3.08V (PT7A7513, 7523, 7533) - 2.93V (PT7A7514, 7524, 7534) - 2.63V (PT7A7515, 7525, 7535)
200ms reset pulse width Debounced TTL/CMOS-compatible manual-
reset input Independent watchdog timer 1.6sec time-out (not
available for PT7A7531 - 7535) Reset output signal:
- Active-low only (PT7A7511 - 7515)
- Active-high only (PT7A7521 - 7525)
- Active-high and active-low (PT7A7531 - 7535)
Voltage monitor for power-fail or low battery
warning
Guaranteed RESET/RESET valid at VCC=1.2V
Description
The PT7A751X/752X/753X family microprocessor (P) supervisory circuits are targeted to improve reliability and accuracy of power-supply circuitry in P’s systems. These devices reduce the complexity and number of components required to monitor power-supply and battery functions.
The main functions are: 1. Asserting reset output during power-up, power-
down and brownout conditions for P system.
2. Detecting power failure or low-battery conditions with a 1.25V threshold detector.
3. Watchdog functions (not for PT7A753x)
Applications
Power-supply circuitry in P systems
PT7A7511P-7515P
Pin ConfPiTg7uAr7a51ti1oWn-7515W
8-Pin PDIP/8-Pin SOIC
PT7A7521P-7525P PT7A7521W-7525W 8-Pin PDIP/8-Pin SOIC
PT7A7531P-7535P PT7A7531W-7535W 8-Pin PDIP/8-Pin SOIC
MR V CC GND PFI
1 2 3 4
8 WDO
MR 1
7 RESET V CC 2
6 WDI
GND 3
5 PFO
PFI 4
8 WDO
MR 1
7 RESET V CC 2
6 WDI
GND 3
5 PFO
PFI 4
8 RESET 7 RESET 6 NC 5 PFO
PT7A7511W-7515W
Top View PT7A7521W-7525W
PT7A7531W-7535W
2014-03-0004
PT0082-9
03/26/14
1
PT7A7511-15/7521-25/7531-35
μP Supervisor Circuits
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Pin Description
Pin Type
Description
MR
I
Manual-Reset: triggers a reset pulse when pulled below 0.8V, active low. It has an internal 250µA pullup current and be driven from a TTL or CMOS logic line as well as shorted to ground with a switch.
VCC Power Supply Voltage.
GND Ground Ground Reference for all signals.
PFI
I
Power-Fail Voltage Monitor Input. When PFI is less than 1.25V, PFO goes low. Connect PFI to GND or Vcc when not used.
PFO O Power-Fail Output: it gets low and sinks current when PFI is less than 1.25V; otherwise PFO stays high.
WDI RESET WDO RESET
Watchdog Input: If WDI remains high or low for 1.6sec, the internal watchdog timer runs out and WDO
I goes low. Floating WDI or connecting WDI to a high-impedance three-state buffer disables the watchdog feature. The internal watchdog timer clears whenever reset is asserted. WDI is three-stated, or WDI sees a
rising or falling edge.
Reset Output pulses: low for 200ms when triggered, and stays low whenever Vcc is below the reset O threshold. It remains low for 200ms after Vcc rises above the reset threshold or MR goes from low to high.
A watchdog timeout will not trigger RESET unless WDO is connected to MR.
Watchdog Output: pulls low when the internal watchdog timer finishes its 1.6sec count and does not go
O
high again until the watchdog is cleared. WDO also goes low during low-line conditions. Whenever Vcc is below the reset threshold, WDO stays low; however, unlike RESET, WDO does not have minimum pulse
width. As soon as Vcc rises above the reset threshold, WDO goes high with no delay.
O The inverse of RESET, active high. Whenever RESET is high, RESET is low.
Block Diagram
Block Diagram of PT7A7511-7515/7521-7525
WDI
MR Vcc PFI
Watchdog Transition Detector
Vcc 250uA
Watchdog Timer
Timebase for Reset & Watchdog
Reset Generator
VRST 1.25V
WDO
RESET (RESET)
PFO
2014-03-0004
PT0082-9
03/26/14
2
PT7A7511-15/7521-25/7531-35 μP Supervisor Circuits
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