Document
CLC5956 12-bit, 65 MSPS Broadband Monolithic A/D Converter
June 1999
CLC5956 12-bit, 65 MSPS Broadband Monolithic A/D Converter
General Description
The CLC5956 is a monolithic 12-bit, 65 MSPS analog-to-digital converter subsystem. The device has been optimized for use in cellular base stations and other applications where high resolution, high sampling rate, wide dynamic range, low power dissipation, and compact size are required. The CLC5956 features differential analog inputs, low jitter differential PECL clock inputs, a low distortion track-and-hold with DC to 300 MHz input bandwidth, a bandgap voltage reference, TTL compatible CMOS output logic, and a proprietary 12-bit multi-stage quantizer. The CLC5956 is fabricated on the ABIC-IV 0.8 micron BiCMOS process. The part features a 73 dB spurious free dynamic range (SFDR) and 67 dB SNR. The wideband track-and-hold allows sampling of IF signals to greater than 250 MHz. The part produces two-tone, dithered, spurious-free dynamic range of 83 dBFS at 75 MHz input frequency. The differential analog input provides excellent common-mode rejection, while the differential PECL clock inputs permit the use of balanced transmission to minimize jitter in distributed systems. The 48-pin TSSOP package provides an extremely small footprint for applications where space is a critical consideration. The CLC5956 operates from a single +5V power supply over the industrial temperature range of −40˚C to +85˚C. National thoroughly tests each part to verify full compliance with the guaranteed specifications.
Features
n n n n n n Wide dynamic range IF sampling capability 300 MHz input bandwidth Small 48-pin TSSOP Single +5V supply Low cost
Key Specifications
n n n n n Sample Rate SFDR SFDR with dither SNR Low power consumption 65 MSPS 73 dBc 85 dBFS 67 dB 615 mW
Applications
n n n n n n n n Cellular base-stations Digital communications Infrared/CCD imaging IF sampling Electro-optics Instrumentation Medical imaging High definition video
Block Diagram
DS015011-2
© 1999 National Semiconductor Corporation
DS015011
www.national.com
Pin Configuration
Ordering Information
CLC5956IMTD CLC5956IMTDX CLC5956PCASM 48-Pin TSSOP 48-Pin TSSOP (Taped Reel) Evaluation Board
DS015011-1
Pin Descriptions
Pin Name AIN AIN ENCODE ENCODE Pin No. 13, 14 Description Differential input with a common mode voltage of +2.4V. The ADC full scale input is 1.024 VPP on each of the complimentary input signals. Differential clock where ENCODE initiates a new data conversion cycle on each rising edge. Logic for these inputs are a 50% duty cycle differential PECL signal. Internal common mode voltage reference. Nominally +2.4V. Can be used for the input common mode voltage. This voltage is derived from an internal bandgap reference. Digital data outputs are CMOS and TTL compatible. D0 is the LSB and D11 is the MSB. MSB is inverted. Output coding is two’s complement. Circuit ground. +5V power supply for the analog section. Bypass to ground with .