MACH221SP

MACH 1 and 2 CPLD Families High-Performance EE CMOS Programmable Logic FEATURES x High-performance electrically-erasable CMOS PLD families x 32 to 128 macrocells x 44 to 100 pins in cost-effective PLCC, PQFP and TQFP packages x SpeedLocking™ – guaranteed fixed timing up to 16 product terms x Commercial 5/5.5/6/7.5/10/12/15-ns tPD and Industrial 7.5/10/12/14/18-ns tPD x Configurable macrocells — Programmable polarity — Registered or combinatorial outputs — Internal and I/O feedback paths — D-type or T-type flip-flops — Output Enables — Choice of clocks for each flip-flop — Input registers for MACH 2 family x JTAG (IEEE 1149.1)-compatible, 5-V in-system programming available x Peripheral component interconnect (PCI) compliant at 5/5.5/6/7.5/10/12 ns x Safe for mixed supply voltage system designs x Bus-Friendly™ inputs and I/Os reduce risk of unwanted oscillatory outputs x Programmable power-down mode results in power savings of up to 75% x Supported by Vantis DesignDirect™ software for rapid logic development — Supports HDL design methodologies with results optimized for Vantis — Flexibility to adapt to user requirements — Software partnerships that ensure customer success x Lattice/Vantis and third-party hardware programming support — Lattice/VantisPRO™ (formerly known as MACHPRO®) software for in-system programmability support on PCs and Automated Test Equipment — Programming support on all major programmers including Data I/O, BP Microsystems, Advin, and System General Publicatio...