BBT3821

® Data Sheet July 20, 2005 BBT3821 FN7483.2 Octal 2.488Gbps to 3.187Gbps/ Lane Retimer 0.13mm Pure-Digital CMOS Technology 1.5V Core Supply, Control I/O 2.5V Tolerant Features 8 Lanes of Clock & Data Recovery and Retiming; 4 in Each Direction Differential Input/Output Wide Operating Data Rate Range: 2.488Gbps to 3.1875Gbps, and 1.244Gbps to 1.59325Gbps Ultra Low-Power Operation (195mW typical per lane, 1550mW typical total consumption) Low Power Version Available for LX4 Applications 17mm Square Low Profile 192 pin 1.0mm Pitch EBGA Package Compliant to the IEEE 802.3 10GBASE-LX4(WWDM), 10GBASE-CX4, and XAUI Specifications Reset Jitter Domain Meets 802.3ae and 802.3ak Jitter Requirements with Significant Margin Received Data Aligned to Local Reference Clock for Retransmission Increase Driving Distance LX4: Up to 40 inches of FR-4 Traces or 500 Meters of MMF Fiber at 3.1875Gbps CX4: Over 15 meters of Compatible Cable Clock Compensation Tx/Rx Rate Matching via IDLE Insertion/Deletion up to ±100ppm Clock Difference Receive Signal Detect and 16 Levels of Receiver Equalization for Media Compensation CML CX4 Transmission Output with 16 Settable Levels of Pre-Emphasis, Eight on XAUI Side Single-Ended or Differential Input Lower-Speed Reference Clock Ease of Testing Complete Suite of Ingress-Egress Loopbacks Full 802.3ae Pattern Generation and Test, including CJPAT & CRPAT PRBS (both 223-1 and 13458 byte) Built-In Self Tests, Error...