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840002I Dataheets PDF



Part Number 840002I
Manufacturers IDT
Logo IDT
Description Crystal-to-LVCMOS/LVTTL Frequency Synthesizer
Datasheet 840002I Datasheet840002I Datasheet (PDF)

FemtoClocks™ Crystal-to-LVCMOS/ LVTTL Frequency Synthesizer 840002I DATASHEET GENERAL DESCRIPTION The 840002I is a 2 output LVCMOS/LVTTL Synthesizer optimized to generate Fibre Channel reference clock frequencies. Using a 26.5625MHz 18pF parallel resonant crystal, the following frequencies can be generated based on the 2 frequency select pins (F_SEL1:0): 212.5MHz, 159.375MHz, 156.25MHz, 106.25MHz, and 53.125MHz. The 840002I uses IDT’s 3rd generation low phase noise VCO technology and can achie.

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FemtoClocks™ Crystal-to-LVCMOS/ LVTTL Frequency Synthesizer 840002I DATASHEET GENERAL DESCRIPTION The 840002I is a 2 output LVCMOS/LVTTL Synthesizer optimized to generate Fibre Channel reference clock frequencies. Using a 26.5625MHz 18pF parallel resonant crystal, the following frequencies can be generated based on the 2 frequency select pins (F_SEL1:0): 212.5MHz, 159.375MHz, 156.25MHz, 106.25MHz, and 53.125MHz. The 840002I uses IDT’s 3rd generation low phase noise VCO technology and can achieve 1ps or lower typical rms phase jitter, easily meeting Fibre Channel jitter requirements. The 840002I is packaged in a 16-pin TSSOP package. FREQUENCY SELECT FUNCTION TABLE FEATURES • Two LVCMOS outputs @ 3.3V, 17Ω typical output impedance • Selectable crystal oscillator interface or LVCMOS single-ended input • Output frequency range: 46.66MHz - 233.33MHz • VCO range: 560MHz - 700MHz • Supports the following output frequencies: 212.5MHz, 159.375MHz, 156.25MHz, 106.25MHz and 53.125MHz • RMS phase jitter @ 212.5MHz (637KHz - 10MHz): 0.83ps (typical) Typical phase noise at 212.5MHz: Offset Noise Power 100Hz ................-91.3 dBc/Hz 1KHz ..............-114.3 dBc/Hz 10KHz ..............-120.7 dBc/Hz 100KHz ..............-120.2 dBc/Hz • Power supply modes: Core/Output 3.3V/3.3V 3.3V/2.5V 2.5V/2.5V • -40°C to 85°C ambient operating temperature • Lead-Free package RoHS compliant Input Frequency (MHz) F_SEL1 26.5625 0 26.5625 0 26.5625 1 26.5625 1 26.04166 0 BLOCK DIAGRAM F_SEL0 0 1 0 1 1 Inputs M Divider Value N Divider Value 24 3 24 4 24 6 24 12 24 4 Output Frequency M/N Ratio Value (MHz) 8 212.5 6 159.375 4 106.25 2 53.125 6 156.25 PIN ASSIGNMENT F_SEL0 nXTAL_SEL TEST_CLK OE MR nPLL_SEL VDDA VDD 1 2 3 4 5 6 7 8 16 F_SEL1 15 GND 14 GND 13 Q0 12 Q1 11 VDDO 10 XTAL_IN 9 XTAL_OUT 840002I 16-Lead TSSOP 4.4mm x 5.0mm x 0.92mm package body G Package Top View 840002I REVISION A 3/30/15 1 ©2015 Integrated Device Technology, Inc. 840002I DATA SHEET TABLE 1. PIN DESCRIPTIONS Number Name Type Description 1, 16 F_SEL0, F_ SEL1 Input Pullup Frequency select pins. LVCMOS/LVTTL interface levels. Selects between the crystal or TEST_CLK inputs as the PLL reference 2 nXTAL_SEL Input Pulldown source. When HIGH, selects TEST_CLK. When LOW, selects XTAL inputs. LVCMOS/LVTTL interface levels. 3 TEST_CLK Input Pulldown Single-ended LVCMOS/LVTTL clock input. 4 OE Input Pullup Output enable pin. When HIGH, the outputs are active. When LOW, the outputs are in a high impedance state. LVCMOS/LVTTL interface levels. Active HIGH Master Reset. When logic HIGH, the internal dividers are 5 MR Input Pulldown reset causing active outputs to go low. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS/LVTTL interface levels. PLL Bypass. When LOW, the output is driven from the VCO output. 6 nPLL_SEL Input Pulldown When HIGH, the PLL is bypassed and the output frequency = reference clock frequency/n output divider. LVCMOS/LVTTL interface levels. 7 V Power DDA 8 VDD Power 9, 10 XTAL_OUT, XTAL_IN Input Analog supply pin. Core supply pin. Crystal oscillator interface. XTAL_IN is the input. XTAL_OUT is the output. 11 12, 13 V DDO Q1, Q0 Power Output Output supply pin. Single-ended clock outputs. LVCMOS/LVTTL interface levels. 14, 15 GND Power Power supply ground. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol CIN CPD RPULLUP RPULLDOWN Parameter Input Capacitance Power Dissipation Capacitance Input Pullup Resistor Input Pulldown Resistor ROUT Output Impedance Test Conditions 3.3V±5% 2.5V±5% Minimum 14 16 Typical 4 8 51 51 17 21 Maximum 21 25 Units pF pF kΩ kΩ Ω Ω TABLE 3. FREQUENCY SELECT FUNCTION TABLE Input Frequency (MHz) 26.5625 26.5625 26.5625 26.5625 26.04166 F_SEL1 0 0 1 1 0 F_SEL0 0 1 0 1 1 Inputs M Divider Value N Divider Value 24 3 24 4 24 6 24 12 24 4 M/N Divider Value 8 6 4 2 6 Output Frequency (MHz) 212.5 159.375 106.25 53.125 156.25 FEMTOCLOCKS™ CRYSTAL-TOLVCMOS/ LVTTL FREQUENCY SYNTHESIZER 2 REVISION A 3/30/15 840002I DATA SHEET ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5 V Outputs, VO -0.5V to VDD + 0.5V Package Thermal Impedance, θJA 89°C/W (0 lfpm) Storage Temperature, TSTG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, VDDO = 3.3V±5% OR 2.5V±5%, TA = -40°C TO 85°C Symbol VDD VDDA Parameter Core Supply Voltage Analog Supply Voltage V.


AN32055A 840002I ICS840002I-01


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