74LVX125

74LVX125 Low-Voltage Quad Buffer with TRI-STATE Outputs January 1996 74LVX125 Low-Voltage Quad Buffer with TRI-STATE Outputs General Description The LVX125 contains four independent non-inverting buffers with TRI-STATE outputs The inputs tolerate voltages up to 7V allowing the interface of 5V systems to 3V systems Features Y Input voltage level translation from 5V to 3V Y Ideal for low power low noise 3 3V applications Y Available in SOIC JEDEC SOIC EIAJ and TSSOP packages Y Guaranteed simultaneous switching noise level and dy- namic threshold performance Logic Symbol Connection Diagram IEEE IEC Pin Assignment for SOIC and TSSOP TL F 12007 – 1 Truth Table Pin Names An Bn On Description Inputs Outputs Inputs An Bn LL LH HX H e HIGH Voltage Level L e LOW Voltage Level Z e High Impedance X e Immaterial Output On L H Z Order Number See NS Package Number SOIC JEDEC 74LVX125M 74LVX125MX M14A SOIC EIAJ 74LVX125SJ 74LVX125SJX M14D TL F 12007 – 2 TSSOP 74LVX125MTC 74LVX125MTCX MTC14 TRI-STATE is a registered trademark of National Semiconductor Corporation C1996 National Semiconductor Corporation TL F 12007 RRD-B30M17 Printed in U S A http www national com Absolute Maximum Ratings (Note) If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Supply Voltage (VCC) b0 5V to a7 0V DC Input Diode Current (IIK) VI e b0 5V b20 mA DC Input Voltage (VI) b0 5V to a7 ...