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IS43LR32800G Dataheets PDF



Part Number IS43LR32800G
Manufacturers ISSI
Logo ISSI
Description 2M x 32Bits x 4Banks Mobile DDR SDRAM
Datasheet IS43LR32800G DatasheetIS43LR32800G Datasheet (PDF)

IS43LR32800G, IS46LR32800G 2M x 32Bits x 4Banks Mobile DDR SDRAM Description The IS43/46LR32800G is 268,435,456 bits CMOS Mobile Double Data Rate Synchronous DRAM organized as 4 banks of 2,097,152 words x 32 bits. This product uses a double-data-rate architecture to achieve high-speed operation. The Data Input/ Output signals are transmitted on a 32-bit bus. The double data rate architecture is essentially a 2N prefetch architecture with an interface designed to transfer two data words per cloc.

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IS43LR32800G, IS46LR32800G 2M x 32Bits x 4Banks Mobile DDR SDRAM Description The IS43/46LR32800G is 268,435,456 bits CMOS Mobile Double Data Rate Synchronous DRAM organized as 4 banks of 2,097,152 words x 32 bits. This product uses a double-data-rate architecture to achieve high-speed operation. The Data Input/ Output signals are transmitted on a 32-bit bus. The double data rate architecture is essentially a 2N prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. This product offers fully synchronous operations referenced to both rising and falling edges of the clock. The data paths are internally pipelined and 2n-bits prefetched to achieve very high bandwidth. All input and output voltage levels are compatible with LVCMOS. Features • JEDEC standard 1.8V power supply. • VDD = 1.8V, VDDQ = 1.8V • Four internal banks for concurrent operation • MRS cycle with address key programs - CAS latency 2, 3 (clock) - Burst length (2, 4, 8, 16) - Burst type (sequential & interleave) • Fully differential clock inputs (CK, /CK) • All inputs except data & DM are sampled at the rising edge of the system clock • Data I/O transaction on both edges of data strobe • Bidirectional data strobe per byte of data (DQS) • DM for write masking only • Edge aligned data & data strobe output • Center aligned data & data strobe input • 64ms refresh period (4K cycle) • Auto & self refresh • Concurrent Auto Precharge • Maximum clock frequency up to 200MHZ • Maximum data rate up to 400Mbps/pin • Power Saving support - PASR (Partial Array Self Refresh) - Auto TCSR (Temperature Compensated Self Refresh) - Deep Power Down Mode - Programmable Driver Strength Control by Full Strength or 3/4, 1/2, 1/4, 1/8 of Full Strength • Status Register Read (SRR) • LVCMOS compatible inputs/outputs • Packages: - 90-Ball BGA -152-Ball PoP BGA Copyright © 2013 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized; b.) the user assume all such risks; and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Rev. A | November 2013 www.issi.com - [email protected] 1 IS43LR32800G, IS46LR32800G Figure 1: 90Ball FBGA Ball Assignment 1 2 3 456 7 8 9 A VSS DQ31 VSSQ B VDDQ DQ29 DQ30 C VSSQ DQ27 D VDDQ DQ25 DQ28 DQ26 E VSSQ DQS3 DQ24 F VDD DM3 NC G CKE CLK /CLK H A9 A11 NC J A6 A7 A8 K A4 DM1 A5 L VSSQ DQS1 DQ8 M VDDQ DQ9 N VSSQ DQ11 DQ10 DQ12 P VDDQ DQ13 DQ14 R VSS DQ15 VSSQ VDDQ DQ16 VDD DQ17 DQ18 VSSQ DQ19 DQ20 VDDQ DQ21 DQ22 VSSQ DQ23 DQS2 VDDQ NC DM2 VSS /WE /CAS /RAS /CS BA0 BA1 A10 A0 A1 A2 DM0 A3 DQ7 DQS0 VDDQ DQ5 DQ6 VSSQ DQ3 DQ4 VDDQ DQ1 DQ2 VSSQ VDDQ DQ0 VDD [Top View] Rev. A | November 2013 www.issi.com - [email protected] 2 Figure 2: 152-Ball VFBGA Ball Assignment IS43LR32800G, IS46LR32800G [Top View] Notes: 1. Although not bonded to the die, these pins may be connected on the package substrate. 2. A12 (R21) is used for 1Gb (32Mx32) and 512Mb (16Mx32), and is NC for 256Mb (8mx32). Rev. A | November 2013 www.issi.com - [email protected] 3 IS43LR32800G, IS46LR32800G Table2 : Pin Descriptions Symbol Type CK, /CK Input CKE Input /CS Input BA0, BA1 Input A0~A11 /RAS, /CAS, /WE DM0~DM3 Input Input Input Function System Clock Clock Enable Chip Select Bank Address Address Row Address Strobe, Column Address Strobe, Write Enable Data Input Mask Descriptions The system clock input. CK and /CK are differential clock inputs. All address and control input signals are registered on the crossing of the rising edge of CK and falling edge of /CK. Input and output data is referenced to the crossing of CK and /CK. CKE is clock enable controls input. CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device input buffers and output drivers. CKE is synchronous for all functions except for SELF REFRESH EXIT, which is achieved asynchronously. /CS enables (registered Low) and disables (registered High) the command decoder. All commands are masked when /CS IS REGISTERED high. /CS provides for external bank selection .


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