IS46LR32160B

IS43LR32160B, IS46LR32160B 4M x 32Bits x 4Banks Mobile DDR SDRAM Description The IS43/46LR32160B is 536,870,912 bits CMOS Mobile Double Data Rate Synchronous DRAM organized as 4 banks of 4,194,304 words x 32 bits. This product uses a double-data-rate architecture to achieve high-speed operation. The Data Input/ Output signals are transmitted on a 32-bit bus. The double data rate architecture is essentially a 2N prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. This product offers fully synchronous operations referenced to both rising and falling edges of the clock. The data paths are internally pipelined and 2n-bits prefetched to achieve very high bandwidth. All input and output voltage levels are compatible with LVCMOS. Features JEDEC standard 1.8V power supply. VDD = 1.8V, VDDQ = 1.8V Four internal banks for concurrent operation MRS cycle with address key programs - CAS latency 2, 3 (clock) - Burst length (2, 4, 8, 16) - Burst type (sequential & interleave) Fully differential clock inputs (CK, /CK) All inputs except data & DM are sampled at the rising edge of the system clock Data I/O transaction on both edges of data strobe Bidirectional data strobe per byte of data (DQS) DM for write masking only Edge aligned data & data strobe output Center aligned data & data strobe input 64ms refresh period (8K cycle) Auto & self refresh Concurrent Auto Precharge Maximum clock frequency up to 1...