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IS46LD32160A Dataheets PDF



Part Number IS46LD32160A
Manufacturers ISSI
Logo ISSI
Description 512Mb Mobile LPDDR2 S4 SDRAM
Datasheet IS46LD32160A DatasheetIS46LD32160A Datasheet (PDF)

IS43/46LD16320A IS43/46LD32160A 512Mb (x16, x32) Mobile LPDDR2 S4 SDRAM FEATURES • Low-voltage Core and I/O Power Supplies VDD2 = 1.14-1.30V, VDDCA/VDDQ = 1.14-1.30V, VDD1 = 1.70-1.95V • High Speed Un-terminated Logic(HSUL_12) I/O Interface • Clock Frequency Range : 10MHz to 533MHz (data rate range : 20Mbps to 1066Mbps per I/O) • Four-bit Pre-fetch DDR Architecture • Multiplexed, double data rate, command/address inputs • Four internal banks for concurrent operation • Bidirectional/dif.

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IS43/46LD16320A IS43/46LD32160A 512Mb (x16, x32) Mobile LPDDR2 S4 SDRAM FEATURES • Low-voltage Core and I/O Power Supplies VDD2 = 1.14-1.30V, VDDCA/VDDQ = 1.14-1.30V, VDD1 = 1.70-1.95V • High Speed Un-terminated Logic(HSUL_12) I/O Interface • Clock Frequency Range : 10MHz to 533MHz (data rate range : 20Mbps to 1066Mbps per I/O) • Four-bit Pre-fetch DDR Architecture • Multiplexed, double data rate, command/address inputs • Four internal banks for concurrent operation • Bidirectional/differential data strobe per byte of data (DQS/DQS#) • Programmable Read/Write latencies(RL/WL) and burst lengths(4,8 or 16) • ZQ Calibration • On-chip temperature sensor to control self refresh rate • Partial –array self refresh(PASR) • Deep power-down mode(DPD) • Operation Temperature Commercial (TC = 0°C to 85°C) Industrial (TC = -40°C to 85°C) Automotive, A1 (TC = -40°C to 85°C) Automotive, A2 (TC = -40°C to 105°C) OPTIONS • Configuration: − 32Mx16 (8M x 16 x 4 banks) − 16Mx32 (4M x 32 x 4 banks) Package: − 134-ball BGA for x16 / x32 − 168-ball PoP BGA for x32 DESCRIPTION MAY 2016 The IS43/46LD16320A/32160A is 512Mbit CMOS LPDDR2 DRAM. The device is organized as 4 banks of 8Meg words of 16bits or 4Meg words of 32bits. This product uses a double-data-rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 4N prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. This product offers fully synchronous operations referenced to both rising and falling edges of the clock. The data paths are internally pipelined and 4n bits prefetched to achieve very high bandwidth. ADDRESS TABLE Parameter Row Addresses Column Addresses Bank Addresses Refresh Count 16Mx32 R0-R12 C0-C8 BA0-BA1 4096 32Mx16 R0-R12 C0-C9 BA0-BA1 4096 KEY TIMING PARAMETERS(1) Speed Grade -18 Data Rate (Mb/s) 1066 Write Read tRCD/ Latency Latency tRP(2) 4 8 Typical -25 800 3 6 Typical -3 667 2 5 Typical Notes: 1. Other clock frequencies/data rates supported; please refer to AC timing tables. 2. Please contact ISSI for Fast trcd/trp. Copyright © 2016 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized; b.) the user assume all such risks; and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc. — www.issi.com 1 Rev. A 05/02/2016 IS43/46LD16320A IS43/46LD32160A BALL ASSIGNMENTS AND DESCRIPTIONS 134-ball FBGA (x32), 0.65mm pitch 1 A DNU B DNU C VDD1 D VSS E VSSCA F VDDCA G VDD2 H VDDCA J VSSCA K CKE L CS# M CA4 N VSSCA P VSS R VDD1 T DNU U DNU 1 2 DNU NC VSS VDD2 CA9 CA6 CA5 VSS NC RFU RFU CA3 VDDCA VDD2 VSS NC DNU 2 3 NC RFU ZQ CA8 CA7 Vref(CA) CK# CK RFU RFU CA2 CA1 CA0 NC NC 3 4 4 56 VDD2 VSS VDDQ DQ28 VSSQ DQS1# DM1 VSSQ DM0 DQS0# VSSQ DQ19 VDDQ VSS VDD2 VDD1 VSSQ DQ30 DQ24 DQ11 DQS1 VDDQ VDDQ VDDQ DQS0 DQ4 DQ23 DQ17 VSSQ VDD1 56 7 DQ31 VDDQ DQ27 DM3 DQ13 DQ10 VDD2 DQ5 DQ2 DM2 DQ20 VDDQ DQ16 7 8 DQ29 DQ25 DQS3 DQ15 DQ14 DQ9 VSS DQ6 DQ1 DQ0 DQS2 DQ22 DQ18 8 9 DNU DQ26 VSSQ DQS3# VDDQ DQ12 DQ8 Vref(DQ) DQ7 DQ3 VDDQ DQS2# VSSQ DQ21 DNU 9 10 DNU DNU VDDQ VSSQ VSSQ VDDQ VSSQ VSSQ VDDQ VSSQ VSSQ VDDQ DNU DNU 10 A B C D E F G H J K L M N P R T U DQ CA Power Ground No ball ZQ Clock NC, DNU, RFU Top View (ball down) Integrated Silicon Solution, Inc. — www.issi.com 2 Rev. A 05/02/2016 IS43/46LD16320A IS43/46LD32160A BALL ASSIGNMENTS AND DESCRIPTIONS 134-ball FBGA (x16), 0.65mm pitch 123 A DNU DNU B DNU NC NC C VDD1 VSS RFU D VSS VDD2 ZQ E VSSCA CA9 CA8 F VDDCA CA6 CA7 G VDD2 CA5 Vref(CA) H VDDCA VSS CK# J VSSCA NC CK K CKE RFU RFU L CS# RFU RFU M CA4 CA3 CA2 N VSSCA VDDCA CA1 P VSS VDD2 CA0 R VDD1 VSS NC T DNU U DNU NC DNU NC 123 4 4 5 VDD2 VSS VDDQ NC VSSQ DQS1# DM1 VSSQ DM0 DQS0# VSSQ NC VDDQ VSS VDD2 5 6 VDD1 VSSQ NC NC DQ11 DQS1 VDDQ VDDQ VDDQ DQS0 DQ4 NC NC VSSQ VDD1 6 7 NC VDDQ NC NC DQ13 DQ10 VDD2 DQ5 DQ2 NC NC VDDQ NC 7 8 NC NC NC DQ15 DQ14 DQ9 VSS DQ6 DQ1 DQ0 NC NC NC 8 9 DNU NC VSSQ NC VDDQ DQ12 DQ8 10 DNU DNU VDDQ VSS.


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