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165-Bump BGA Commercial Temp Industrial Temp
GS8342Q08/09/18/36BD-357/333/300/250
36Mb SigmaQuad-IITM Burst of 2 SRAM
357 MHz–250 MHz 1.8 V VDD
1.8 V and 1.5 V I/O
Features
• Simultaneous Read and Write SigmaQuad™ Interface • JEDEC-standard pinout and package • Dual Double Data Rate interface • Byte Write controls sampled at data-in time • Burst of 2 Read and Write • 1.8 V +100/–100 mV core power supply • 1.5 V or 1.8 V HSTL Interface • Pipelined read operation • Fully coherent read and write pipelines • ZQ pin for programmable output drive strength • IEEE 1149.1 JTAG-compliant Boundary Scan • Pin-compatible with present 144 Mb devices • 165-bump, 13 mm x 15 mm, 1 mm bump pitch BGA package • RoHS-compliant 165-bump BGA package available
SigmaQuad™ Family Overview
The GS8342Q08/09/18/36BD are built in compliance with the SigmaQuad-II SRAM pinout standard for Separate I/O synchronous SRAMs. They are 37,748,736-bit (36Mb) SRAMs. The GS8342Q08/09/18/36BD SigmaQuad SRAMs are just one element in a family of low power, low voltage HSTL I/O SRAMs designed to operate at the speeds needed to implement economical high performance networking systems.
Clocking and Addressing Schemes
The GS8342Q08/09/18/36BD SigmaQuad-II SRAMs are synchronous devices. They employ two input register clock inputs, K and K. K and K are independent single-ended clock inputs, not differential inputs to a single differential clock input buffer. The device also allows the user to manipulate the output register clock inputs quasi independently with the C and C clock inputs. C and C are also independent single-ended clock inputs, not differential inputs. If the C clocks are tied high, the K clocks are routed internally to fire the output registers instead.
Each internal read and write operation in a SigmaQuad-II B2 RAM is two times wider than the device I/O bus. An input data bus de-multiplexer is used to accumulate incoming data before it is simultaneously written to the memory array. An output data multiplexer is used to capture the data produced from a single memory array read and then route it to the appropriate output drivers as needed. Therefore the address field of a SigmaQuad-II B2 RAM is always one address pin less than the advertised index depth (e.g., the 4M x 8 has an 2M addressable index).
tKHKH tKHQV
Parameter Synopsis
-357 2.8 ns 0.45 ns
-333 3.0 ns 0.45 ns
-300 3.3 ns 0.45 ns
-250 4.0 ns 0.45 ns
Rev: 1.02b 4/2014
1/34
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology
GS8342Q08/09/18/36BD-357/333/300/250
1M x 36 SigmaQuad-II SRAM—Top View
1 2 3 4 5 6 7 8 9 10 11
A
CQ
NC/SA NC/SA (288Mb) (72Mb)
W
BW2
K
BW1
R
SA
NC/SA (144Mb)
CQ
B Q27 Q18 D18 SA BW3 K BW0 SA D17 Q17 Q8
C D27 Q28 D19 VSS SA SA SA VSS D16 Q7 D8
D D28 D20 Q19 VSS VSS VSS VSS VSS Q16 D15 D7
E
Q29
D29
Q20
VDDQ
VSS
VSS
VSS
VDDQ
Q15
D6
Q6
F
Q30 Q21 D21
VDDQ
VDD
VSS
VDD
VDDQ
D14
Q14
Q5
G
D30 D22 Q22 VDDQ VDD
VSS
VDD
VDDQ
Q13
D13
D5
H
Doff
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
VREF
ZQ
J
D31
Q31
D23
VDDQ
VDD
VSS
VDD
VDDQ
D12
Q4
D4
K
Q32 D32 Q23 VDDQ VDD
VSS
VDD
VDDQ
Q12
D3
Q3
L
Q33
Q24
D24
VDDQ
VSS
VSS
VSS
VDDQ
D11
Q11
Q2
M D33 Q34 D25 VSS VSS VSS VSS VSS D10 Q1 D2
N
D34 D26 Q25 VSS SA
SA
SA
VSS Q10
D9
D1
P
Q35 D35 Q26
SA
SA
C
SA SA Q9 D0 Q0
R
TDO TCK
SA
SA
SA
C
SA SA SA TMS TDI
11 x 15 Bump BGA—13 x 15 mm Body—1 mm Bump Pitch
Notes: 1. BW0 controls writes to D0:D8; BW1 controls writes to D9:D17; BW2 controls writes to D18:D26; BW3 controls writes to D27:D35. 2. A2, A3, and A10 are the expansion addresses.
Rev: 1.02b 4/2014
2/34
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology
GS8342Q08/09/18/36BD-357/333/300/250
2M x 18 SigmaQuad-II SRAM—Top View
123456789
A
CQ
NC/SA (144Mb)
SA
W
BW1
K
NC/SA (288Mb)
R
SA
B NC Q9 D9 SA NC K BW0 SA NC
C NC NC D10 VSS SA SA SA VSS NC
D NC D11 Q10 VSS VSS VSS VSS VSS NC
E NC NC Q11 VDDQ VSS VSS VSS VDDQ NC
F
NC
Q12
D12
VDDQ
VDD
VSS
VDD VDDQ NC
G
NC
D13
Q13
VDDQ
VDD
VSS
VDD VDDQ NC
H
Doff
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
J
NC
NC
D14
VDDQ
VDD
VSS
VDD VDDQ NC
K NC NC Q14 VDDQ VDD VSS VDD VDDQ NC
L NC Q15 D15 VDDQ VSS VSS VSS VDDQ NC
M NC NC D16 VSS VSS VSS VSS VSS NC
N NC D17 Q16 VSS SA SA SA VSS NC
P NC NC Q17 SA SA C SA SA NC
R
TDO TCK
SA
SA
SA
C
SA SA SA
11 x 15 Bump BGA—13 x 15 mm Body—1 mm Bump Pitch
Notes: 1. BW0 controls writes to D0:D8. BW1 controls writes to D9:D17. 2. A2, A7, and A10 are the expansion addresses.
10 NC/SA (72Mb)
NC Q7 NC D6 NC NC VREF Q4 D3 NC Q1 NC D0 TMS
11 CQ Q8 D8 D7 Q6 Q5 D5 ZQ D4 Q3 Q2 D2 D1 Q0 TDI
Rev: 1.02b 4/2014
3/34
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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