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IS61QDPB22M18A/A1/A2 IS61QDPB21M36A/A1/A2
2Mx18, 1Mx36 36Mb QUADP (Burst 2) Synchronous SRAM
(2.5 CYCLE READ LATENCY)
DECEMBER 2014
FEATURES
1Mx36 and 2Mx18 configuration available.
On-chip Delay-Locked Loop (DLL) for wide data valid window.
Separate independent read and write ports with concurrent read and write operations.
Synchronous pipeline read with EARLY write operation.
Double Data Rate (DDR) interface for read and write input ports.
2.5 Cycle read latency.
Fixed 2-bit burst for read and write operations.
Clock stop support.
Two input clocks (K and K#) for address and control registering at rising edges only.
Two echo clocks (CQ and CQ#) that are delivered simultaneously with data.
DESCRIPTION
The and
are synchronous, high-
performance CMOS static random access memory (SRAM)
devices. These SRAMs have separate I/Os, eliminating the
need for high-speed bus turnaround. The rising edge of K
clock initiates the read/write operation, and all internal
operations are self-timed. Refer to the
for a description of the basic
operations of these
SRAMs. Read and
write addresses are registered on alternating rising edges of
the K clock. Read and write performed in double data rate.
The following are registered internally on the rising edge of the K clock:
Read address
Read enable
Write enable
Data valid pin (QVLD).
Data-in for early writes
+1.8V core power supply and 1.5, 1.8V VDDQ, used with 0.75, 0.9V VREF.
HSTL input and output interface.
Registered addresses, write and read controls, byte writes, data in, and data outputs.
Full data coherency.
The following are registered on the rising edge of the K# clock:
Write address
Byte writes
Data-in for second burst addresses
Boundary scan using limited set of JTAG 1149.1 functions.
Byte Write capability.
Fine ball grid array (FBGA) package option:
13mmx15mm and 15mmx17mm body size 165-ball (11 x 15) array Programmable impedance output drivers via 5x user-supplied precision resistor.
ODT (On Die Termination) feature is supported optionally on data input, K/K#, and BWx#.
The end of top mark (A/A1/A2) is to define options. IS61QDPB21M36A : Don’t care ODT function and pin connection
IS61QDPB21M36A1 : Option1
Byte writes can change with the corresponding data-in to enable or disable writes on a per-byte basis. An internal write buffer enables the data-ins to be registered half a cycle earlier than the write address. The first data-in burst is clocked at the same time as the write command signal, and the second burst is timed to the following rising edge of the K# clock.
During the burst read operation, the data-outs from the first bursts are updated from output registers of the second rising edge of the K# clock (starting two and half cycles later after read command). The data-outs from the second bursts are updated with the third rising edge of the K clock. The K and K# clocks are used to time the data-outs.
IS61QDPB21M36A2 : Option.