18Mb QUADP (Burst 2) Synchronous SRAM
IS61QDPB21M18A/A1/A2 IS61QDPB251236A/A1/A2
1Mx18, 512Kx36 18Mb QUADP (Burst 2) Synchronous SRAM
(2.5 CYCLE READ LATENCY)...
Description
IS61QDPB21M18A/A1/A2 IS61QDPB251236A/A1/A2
1Mx18, 512Kx36 18Mb QUADP (Burst 2) Synchronous SRAM
(2.5 CYCLE READ LATENCY)
OCTOBER 2014
FEATURES
512Kx36 and 1Mx18 configuration available.
On-chip Delay-Locked Loop (DLL) for wide data valid window.
Separate independent read and write ports with concurrent read and write operations.
Synchronous pipeline read with EARLY write operation.
Double Data Rate (DDR) interface for read and write input ports.
2.5 Cycle read latency.
Fixed 2-bit burst for read and write operations.
Clock stop support.
Two input clocks (K and K#) for address and control registering at rising edges only.
Two echo clocks (CQ and CQ#) that are delivered simultaneously with data.
DESCRIPTION
The and
are synchronous, high-
performance CMOS static random access memory (SRAM)
devices. These SRAMs have separate I/Os, eliminating the
need for high-speed bus turnaround. The rising edge of K
clock initiates the read/write operation, and all internal
operations are self-timed. Refer to the
for a description of the basic
operations of these
SRAMs. Read and
write addresses are registered on alternating rising edges of
the K clock. Read and write performed in double data rate.
The following are registered internally on the rising edge of the K clock:
Read address
Read enable
Write enable
Data valid pin (QVLD).
Data-in for early writes
+1.8V core power supply and 1.5, 1.8V VDDQ, used with 0.75, 0.9V VREF.
HSTL input and o...
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