72 Mb (2M x 36. & 4M x 18) QUAD (Burst of 2) Synchronous SRAMs
A May 2009
Features
2M x 36 or 4M x 18.
On-chip delay-locked loop (DLL) for wide data valid window.
Separate read and write ports with concurrent read and write operations.
Synchronous pipeline read with early write operation.
Double data rate (DDR) interface for read and write input ...
