IS61QDPB41M36B1

IS61QDPB42M18B/B1/B2 IS61QDPB41M36B/B1/B2 2Mx18, 1Mx36 36Mb QUADP (Burst 4) SYNCHRONOUS SRAM (2.5 Cycle Read Latency) NOVEMBER 2014 FEATURES DESCRIPTION  1Mx36 and 2Mx18 configuration available.  On-chip Delay-Locked Loop (DLL) for wide data valid window.  Separate independent read and write ports with concurrent read and write operations.  Synchronous pipeline read with late write operation.  Double Data Rate (DDR) interface for read and write input ports.  2.5 cycle read latency.  Fixed 4-bit burst for read and write operations.  Clock stop support.  Two input clocks (K and K#) for address and control registering at rising edges only.  Two echo clocks (CQ and CQ#) that are delivered simultaneously with data.  Data Valid Pin (QVLD).  +1.8V core power supply and 1.5, 1.8V VDDQ, used with 0.75, 0.9V VREF.  HSTL input and output levels.  Registered addresses, write and read controls, byte writes, data in, and data outputs.  Full data coherency.  Boundary scan using limited set of JTAG 1149.1 functions.  Byte write capability.  Fine ball grid array (FBGA) package: 13mmx15mm and 15mmx17mm body size 165-ball (11 x 15) array  Programmable impedance output drivers via 5x user-supplied precision resistor.  ODT (On Die Termination) feature is supported optionally on data input, K/K#, and BWx#.  The end of top mark (B/B1/B2) is to define options. IS61QDPB41M36B : Don’t care ODT function and pin connection IS61QDPB41M36B1 : Option1 IS61QDPB41M36B2 : Option2 Refe...