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IS65WV2568EBLL Dataheets PDF



Part Number IS65WV2568EBLL
Manufacturers ISSI
Logo ISSI
Description ULTRA LOW POWER CMOS STATIC RAM
Datasheet IS65WV2568EBLL DatasheetIS65WV2568EBLL Datasheet (PDF)

IS62WV2568EALL IS62/65WV2568EBLL 256Kx8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM MARCH 2018 KEY FEATURES  High-speed access time: 45ns, 55ns  CMOS low power operation – Operating Current: 18 mA (max) at 85°C – CMOS Standby Current: 5.4uA (typ) at 25°C  TTL compatible interface levels  Single power supply –1.65V-2.2V VDD (IS62WV2568EALL) – 2.2V-3.6V VDD (IS62/65WV2568EBLL)  Three state outputs  Industrial and Automotive temperature support  Lead-free available DESCRIPTION The ISSI .

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IS62WV2568EALL IS62/65WV2568EBLL 256Kx8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM MARCH 2018 KEY FEATURES  High-speed access time: 45ns, 55ns  CMOS low power operation – Operating Current: 18 mA (max) at 85°C – CMOS Standby Current: 5.4uA (typ) at 25°C  TTL compatible interface levels  Single power supply –1.65V-2.2V VDD (IS62WV2568EALL) – 2.2V-3.6V VDD (IS62/65WV2568EBLL)  Three state outputs  Industrial and Automotive temperature support  Lead-free available DESCRIPTION The ISSI IS62/65WV2568EALL/EBLL are high-speed, 2M bit static RAMs organized as 256K words by 8 bits. It is fabricated using ISSI's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields highperformance and low power consumption devices. When CS1# is HIGH (deselected) or when CS2 is LOW (deselected), the device assumes a standby mode at which the power dissipation can be reduced down with CMOS input levels. Easy memory expansion is provided by using Chip Enable and Output Enable inputs. The active LOW Write Enable (WE#) controls both writing and reading of the memory. The IS62/65WV2568EALL/EBLL are packaged in the JEDEC standard 32-pin TSOP (TYPE I), sTSOP (TYPE I), and 36-pin mini BGA.. FUNCTIONAL BLOCK DIAGRAM A0 – A17 VDD GND I/O0 – I/O7 DECODER 256K x 8 MEMORY ARRAY I/O DATA CIRCUIT COLUMN I/O CS2 CS1# OE# WE# CONTROL CIRCUIT Copyright © 2018 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized; b.) the user assume all such risks; and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc.- www.issi.com 1 Rev. B3 03/16/2018 IS62WV2568EALL IS62/65WV2568EBLL PIN CONFIGURATIONS 36-Pin mini BGA (6mm x 8mm) 1 2 3 4 5 6 A A0 A1 CS2 A3 A6 A8 B I/O4 A2 WE# A4 A7 I/O0 C I/O5 NC A5 I/O1 D GND VDD E VDD GND F I/O6 NC A17 I/O2 G I/O7 OE# CS1# A16 A15 I/O3 H A9 A10 A11 A12 A13 A14 32-Pin TSOP (Type I), STSOP (Type I) A11 1 A9 2 A8 3 A13 4 WE# 5 CS2 6 A15 7 VDD 8 A17 9 A16 10 A14 11 A12 12 A7 13 A6 14 A5 14 A4 16 32 OE# 31 A10 30 CS1# 29 I/O7 28 I/O6 27 I/O5 26 I/O4 25 I/O3 24 GND 23 I/O2 22 I/O1 21 I/O0 20 A0 19 A1 18 A2 17 A3 PIN DESCRIPTIONS A0-A17 I/O0-I/O7 CS1#, CS2 OE# WE# NC VDD GND Address Inputs Data Inputs/Outputs Chip Enable Input Output Enable Input Write Enable Input No Connection Power Ground Integrated Silicon Solution, Inc.- www.issi.com 2 Rev. B3 03/16/2018 IS62WV2568EALL IS62/65WV2568EBLL FUNCTION DESCRIPTION SRAM is one of random access memories. SRAM has three different modes supported. Each function is described below with Truth Table. STANDBY MODE Device enters standby mode when deselected (CS1# HIGH or CS2 LOW). The input and output pins (I/O0-7) are placed in a high impedance state. CMOS input in this mode will maximize saving power. WRITE MODE Write operation issues with Chip selected (CS1# LOW and CS2 HIGH) and Write Enable (WE#) input LOW. The input and output pins(I/O0-7) are in data input mode. Output buffers are closed during this time even if OE# is LOW. READ MODE Read operation issues with Chip selected (CS1# LOW and CS2 HIGH) and Write Enable (WE#) input HIGH. When OE# is LOW, output buffer turns on to make data output. Any input to I/O pins during READ mode is not permitted. In the READ mode, output buffers can be turned off by pulling OE# HIGH. In this mode, internal device operates as READ but I/Os are in a high impedance state. Since device is in READ mode, active current is used. TRUTH TABLE Mode CS1# CS2 H X Not Selected X L Output Disabled L H Write L H Read L H WE# X X H H L OE# X X H L X I/O0-I/O7 High-Z High-Z High-Z DIN DOUT VDD Current ISB2 ICC ICC ICC Integrated Silicon Solution, Inc.- www.issi.com 3 Rev. B3 03/16/2018 IS62WV2568EALL IS62/65WV2568EBLL ABSOLUTE MAXIMUM RATINGS AND OPERATING RANGE ABSOLUTE MAXIMUM RATINGS (1) Symbol Parameter Vterm Terminal Voltage with Respect to GND tBIAS Temperature Under Bias VDD VDD.


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