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IDT54FCT377DT Dataheets PDF



Part Number IDT54FCT377DT
Manufacturers Integrated Device Tech
Logo Integrated Device Tech
Description FAST CMOS OCTAL D FLIP-FLOP
Datasheet IDT54FCT377DT DatasheetIDT54FCT377DT Datasheet (PDF)

Integrated Device Technology, Inc. FAST CMOS OCTAL D FLIP-FLOP WITH CLOCK ENABLE IDT54/74FCT377T/AT/CT/DT FEATURES: • Std., A, C and D speed grades • Low input and output leakage ≤1µA (max.) • CMOS power levels • True TTL input and output compatibility – VOH = 3.3V (typ.) – VOL = 0.3V (typ.) • High drive outputs (-15mA IOH, 48mA IOL) • Power off disable outputs permit “live insertion” • Meets or exceeds JEDEC standard 18 specifications • Product available in Radiation Tolerant and Radiation E.

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Integrated Device Technology, Inc. FAST CMOS OCTAL D FLIP-FLOP WITH CLOCK ENABLE IDT54/74FCT377T/AT/CT/DT FEATURES: • Std., A, C and D speed grades • Low input and output leakage ≤1µA (max.) • CMOS power levels • True TTL input and output compatibility – VOH = 3.3V (typ.) – VOL = 0.3V (typ.) • High drive outputs (-15mA IOH, 48mA IOL) • Power off disable outputs permit “live insertion” • Meets or exceeds JEDEC standard 18 specifications • Product available in Radiation Tolerant and Radiation Enhanced versions • Military product compliant to MIL-STD-883, Class B and DESC listed (dual marked) • Available in DIP, SOIC, QSOP, CERPACK and LCC packages DESCRIPTION: The IDT54/74FCT377T/AT/CT/DT are octal D flip-flops built using an advanced dual metal CMOS technology. The IDT54/ 74FCT377T/AT/CT/DT have eight edge-triggered, D-type flipflops with individual D inputs and O outputs. The common buffered Clock (CP) input loads all flip-flops simultaneously when the Clock Enable (CE) is LOW. The register is fully edge-triggered. The state of each D input, one set-up time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop’s O output. The CE input must be stable only one set-up time prior to the LOW-to-HIGH transition for predictable operation. FUNCTIONAL BLOCK DIAGRAM D0 D1 D2 D3 D4 D5 D6 D7 CE DQ CP DQ CP DQ CP DQ CP DQ CP DQ CP DQ CP DQ CP CP O0 O1 O2 O3 O4 O5 O6 O7 2630 drw 01 The IDT logo is a registered trademark of Integrated Device Technology, Inc. MILITARY AND COMMERCIAL TEMPERATURE RANGES ©1995 Integrated Device Technology, Inc. 6.14 APRIL 1995 DSC-4200/3 1 IDT54/74FCT377T/AT/CT/DT FAST CMOS OCTAL D FLIP-FLOP WITH CLOCK ENABLE PIN CONFIGURATIONS CE O0 D0 D1 O1 O2 D2 D3 O3 GND 1 20 2 19 3 P20-1 18 4 D20-1 17 5 SO20-2 16 6 SO20-8 & 15 7 E20-1 14 8 13 9 12 10 11 Vcc O7 D7 D6 O6 O5 D5 D4 O4 CP 2630 drw 02 DIP/SOIC/QSOP/CERPACK TOP VIEW O3 D0 GND O0 CP CE O4 Vcc D4 O7 MILITARY AND COMMERCIAL TEMPERATURE RANGES INDEX 3 2 20 19 D1 4 1 18 D7 O1 5 17 D6 O2 6 L20-2 16 O6 D2 7 15 O5 D3 8 14 D5 9 10 11 12 13 LCC TOP VIEW 2630 drw 03 PIN DESCRIPTION Pin Names Description D0 – D7 CE Data Inputs Clock Enable (Active LOW) O0 – O7 Data Outputs CP Clock Pulse Input 2630 tbl 01 ABSOLUTE MAXIMUM RATINGS(1) Symbol Rating VTERM(2) Terminal Voltage with Respect to GND VTERM(3) Terminal Voltage with Respect to GND TA Operating Temperature TBIAS Temperature Under Bias TSTG Storage Temperature PT Power Dissipation Commercial –0.5 to +7.0 –0.5 to VCC +0.5 0 to +70 –55 to +125 –55 to +125 0.5 Military –0.5 to +7.0 –0.5 to VCC +0.5 –55 to +125 –65 to +135 –65 to +150 0.5 Unit V V °C °C °C W IOUT DC Output –60 to +120 –60 to +120 mA Current NOTES: 2630 lnk 03 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT- INGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other cond.


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