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WM8750JL
Stereo CODEC for Portable Audio Applications
DESCRIPTION
The WM8750JL is a low power, high quality stereo CODEC designed for portable digital audio applications.
The device integrates complete interfaces to stereo or mono microphones and a stereo headphone. External component requirements are drastically reduced as no separate microphone or headphone amplifiers are required. Advanced on-chip digital signal processing performs graphic equaliser, 3-D sound enhancement and automatic level control for the microphone or line input.
The WM8750JL can operate as a master or a slave, with various master clock frequencies including 12 or 24MHz for USB devices, or standard 256fs rates like 12.288MHz and 24.576MHz. Different audio sample rates such as 96kHz, 48kHz, 44.1kHz are generated directly from the master clock without the need for an external PLL.
The WM8750JL operates at supply voltages down to 1.8V, although the digital core can operate at voltages down to 1.42V to save power, and the maximum for all supplies is 3.6 Volts. Different sections of the chip can also be powered down under software control.
The WM8750JL is supplied in a very small and thin 5x5mm QFN package, ideal for use in hand-held and portable systems.
BLOCK DIAGRAM
FEATURES
DAC SNR 97dB (‘A’ weighted), THD -85dB at 48kHz, 3.3V ADC SNR 88dB (‘A’ weighted), THD -80dB at 48kHz, 3.3V Complete Stereo / Mono Microphone Interface
- Programmable ALC (timed out) / Noise Gate On-chip 400mW BTL Speaker Driver (mono) On-chip Headphone Driver
- >40mW output power on 16 / 3.3V - THD –73dB at 5mW, SNR 98dB with 16 load - No DC blocking capacitors required (capless mode) Separately mixed mono output Digital Graphic Equaliser Low Power - 6 mW stereo playback (1.8V / 1.5V supplies) - 13 mW record & playback (1.8V / 1.5V supplies) Low Supply Voltages - Analogue 1.8V to 3.6V - Digital core: 1.42V to 3.6V - Digital I/O: 1.8V to 3.6V 256fs / 384fs or USB master clock rates: 12MHz, 24MHz Audio sample rates: 8, 11.025, 16, 22.05, 24, 32, 44.1, 48, 88.2, 96kHz generated internally from master clock 5x5x0.9mm QFN package
APPLICATIONS
Portable Media Player Mobile phone handsets Mobile gaming
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Production Data, April 2012, Rev 4.1 Copyright 2012 Wolfson Microelectronics plc
WM8750JL
Production Data
TABLE OF CONTENTS
DESCRIPTION ................................................................................................................... 1
FEATURES......................................................................................................................... 1
APPLICATIONS ................................................................................................................. 1
BLOCK DIAGRAM ............................................................................................................. 1
TABLE OF CONTENTS ..................................................................................................... 2
PIN CONFIGURATION....................................................................................................... 3
ORDERING INFORMATION .............................................................................................. 3
PIN DESCRIPTION ............................................................................................................ 4
ABSOLUTE MAXIMUM RATINGS..................................................................................... 5
RECOMMENDED OPERATION CONDITIONS ................................................................. 5
ELECTRICAL CHARACTERISTICS .................................................................................. 6
TYPICAL PERFORMANCE................................................................................................ 8 POWER CONSUMPTION............................................................................................................... 8 OUTPUT DRIVERS ........................................................................................................................ 9 OUTPUT PGA’S LINEARITY ........................................................................................................ 10
SIGNAL TIMING REQUIREMENTS ................................................................................. 11 SYSTEM CLOCK TIMING ............................................................................................................ 11 AUDIO INTERFACE TIMING – MASTER MODE......................................................................... 11 AUDIO INTERFACE TIMING – SLAVE MODE ............................................................................ 12 CONTROL INTERFACE TIMING – 3-WIRE MODE..................................................................... 13 CONTROL INTERFACE TIMING – 2-WIRE MODE.........................................................