IS49NLC18160

IS49NLC93200,IS49NLC18160,IS49NLC36800 288Mb (x9, x18, x36) Common I/O RLDRAM 2 Memory JANUARY 2020 FEATURES  400MHz DDR operation (800Mb/s/pin data rate)  28.8Gb/s peak bandwidth (x36 at 400 MHz clock frequency)  Reduced cycle time (15ns at 400MHz)  32ms refresh (8K refresh for each bank; 64K refresh command must be issued in total each 32ms)  8 internal banks  Non-multiplexed addresses (address multiplexing option available)  SRAM-type interface  Programmable READ latency (RL), row cycle time, and burst sequence length  Balanced READ and WRITE latencies in order to optimize data bus utilization  Data mask signals (DM) to mask signal of WRITE data; DM is sampled on both edges of DK. OPTIONS  Package:  144-ball WBGA (lead-free)  Configuration:  32Mx9  16Mx18  8Mx36  Clock Cycle Timing:  Differential input clocks (CK, CK#)  Differential input data clocks (DKx, DKx#)  On-die DLL generates CK edge-aligned data and output data clock signals  Data valid signal (QVLD)  HSTL I/O (1.5V or 1.8V nominal)  25-60Ω matched impedance outputs  2.5V VEXT, 1.8V VDD, 1.5V or 1.8V VDDQ I/O  On-die termination (ODT) RTT  IEEE 1149.1 compliant JTAG boundary scan  Operating temperature: Commercial (TC = 0° to +95°C; TA = 0°C to +70°C), Industrial (TC = -40°C to +95°C; TA = -40°C to +85°C) Speed Grade -25E -25 -33 -5 Unit tRC 15 20 20 20 ns tCK 2.5 2.5 3.3 5 ns Copyright © 2020 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves th...