Document
Data Sheet
Wideband IF Receiver Subsystem AD6676
FEATURES
APPLICATIONS
High instantaneous dynamic range
Wideband cellular infrastructure equipment and repeaters
Noise figure (NF) as low as 13 dB
Point-to-point microwave equipment
Noise spectral density (NSD) as low as −159 dBFS/Hz
Instrumentation
IIP3 up to 36.9 dBm with spurious tones <−99 dBFS
Spectrum and communication analyzers
Tunable band-pass Σ-Δ analog-to-digital converter (ADC)
Software defined radio
20 MHz to 160 MHz signal bandwidth 70 MHz to 450 MHz IF center frequency Configurable input full-scale level of −2 dBm to −14 dBm
Easy to drive resistive IF input Gain flatness of 1 dB with under 0.5 dB out-of-band peaking
Alias rejection greater than 50 dB 2.0 GSPS to 3.2 GSPS ADC clock rate
On-chip PLL clock multiplier 16-bit I/Q rate up to 266 MSPS On-chip digital signal processing NCO and quadrature digital downconverter (QDDC) Selectable decimation factor of 12, 16, 24, and 32 Automatic gain control (AGC) support On-chip attenuator with 27 dB span in 1 dB steps
GENERAL DESCRIPTION
The AD66761 is a highly integrated IF subsystem that can digitize radio frequency (RF) bands up to 160 MHz in width centered on an intermediate frequency (IF) of 70 MHz to 450 MHz. Unlike traditional Nyquist IF sampling ADCs, the AD6676 relies on a tunable band-pass Σ-Δ ADC with a high oversampling ratio to eliminate the need for band specific IF SAW filters and gain stages, resulting in significant simplification of the wideband radio receiver architecture. On-chip quadrature digital downconversion followed by selectable decimation filters reduces the complex data rate to a manageable rate between 62.5 MSPS to 266.7 MSPS. The 16-bit complex output data is transferred to the host via a single or dual lane JESD204B interface
Fast attenuator control via configurable AGC data port
supporting line rates of up to 5.333 Gbps.
Peak detection flags with programmable thresholds
Single or dual lane, JESD204B capable
Low power consumption: 1.20 W
1.1 V and 2.5 V supply voltage
TDD power saving up to 60%
4.3 mm × 5.0 mm WLCSP
FUNCTIONAL BLOCK DIAGRAM
VSS2IN VSS2OUT VDD2NV
AGC4, AGC3 AGC2, AGC1
VDDIO RESETB
VIN+ VIN–
L+ L–
–2.0V REG 27dB ATTENUATOR (1dB STEPS)
BAND-PASS Σ-∆ ADC
AGC SUPPORT
QDDC + NCO I Q
Mx M = 12, 16, 24,
32
I Q
SPI
CSB SCLK SDIO SDO VDDHSI
SERDOUT0+ SERDOUT0– SERDOUT1+ SERDOUT1–
JESD204B SERIALIZER Tx OUTPUTS
12348-001
CLOCK SYNTHESIZER
CLOCK GENERATION
JESD204B SUBCLASS 1
CONTROL
AD6676
SYNCINB± SYSREF±
VDDQ VDDC CLK+ CLK–
VDD2 VDDL VDD1 VSSA VDDD VSSD
Figure 1.
1 This product is protected by U.S. and international patents.
Rev. D
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AD6676
TABLE OF CONTENTS
Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 3 Product Highlights ........................................................................... 4 Specifications..................................................................................... 5
Digital High Speed SERDES Specifications .............................. 7 CLK± to SYSREF± Timing Diagram ......................................... 8 Digital CMOS Input/Output Specifications ............................. 8 Absolute Maximum Ratings............................................................ 9 Thermal Resistance ...................................................................... 9 ESD Caution.................................................................................. 9 Pin Configuration and Function Descriptions........................... 10 Typical Performance Characteristics ........................................... 12
Nominal Performance for IF = 115 MHz (Direct Sampling
VHF Receiver) ............................................................................ 12
Nominal Performance for IF = 140 MHz (μW Point-to-Point
Receivers).........