AD6673

Data Sheet 80 MHz Bandwidth, Dual IF Receiver AD6673 FEATURES JESD204B Subclass 0 or Subclass 1 coded serial digital outputs Signal-to-noise ratio (SNR) = 71.9 dBFS at 185 MHz AIN and 250 MSPS with NSR set to 33% Spurious-free dynamic range (SFDR) = 88 dBc at 185 MHz AIN and 250 MSPS Total power consumption: 707 mW at 250 MSPS 1.8 V supply voltages Integer 1-to-8 input clock divider Sample rates of up to 250 MSPS IF sampling frequencies of up to 400 MHz Internal analog-to-digital converter (ADC) voltage reference Flexible analog input range 1.4 V p-p to 2.0 V p-p (1.75 V p-p nominal) ADC clock duty cycle stabilizer (DCS) 95 dB channel isolation/crosstalk Serial port control Energy saving power-down modes APPLICATIONS Communications Diversity radio and smart antenna (MIMO) systems Multimode digital receivers (3G) TD-SCDMA, WiMAX, WCDMA, CDMA2000, GSM, EDGE, LTE I/Q demodulation systems General-purpose software radios VIN+A VIN–A VCM VIN+B VIN–B SYSREF± SYNCINB± CLK± RFCLK FUNCTIONAL BLOCK DIAGRAM AVDD DRVDD DVDD AGND DGND DRGND PIPELINE 11-BIT ADC PIPELINE 11-BIT ADC NSR NSR JESD-204B INTERFACE HIGH SPEED SERIALIZERS AD6673 CML, TX OUTPUTS SERDOUT0± SERDOUT1± CLOCK GENERATION CONTROL REGISTERS CMOS DIGITAL INPUT CMOS DIGITAL INPUT/OUTPUT FAST DETECT CMOS DIGITAL OUTPUT PDWN FDA FDB RST SDIO SCLK CS Figure 1. 10632-001 PRODUCT HIGHLIGHTS 1. The configurable JESD204B output block with an integrated phase-locked loop (PLL) to support up to 5 Gbps per lane ...