Seiko Instruments Electronic Components Datasheet


S-1011

VOLTAGE DETECTOR


S-1011 Datasheet PDF
No Preview Available !

Click to Download PDF File for PC

S-1011 Series
www.sii-ic.com
© Seiko Instruments Inc., 2014-2015
HIGH-WITHSTAND VOLTAGE
BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR
Rev.1.2_00
The S-1011 Series is a high-accuracy voltage detector developed using CMOS technology. The detection voltage is fixed
internally, and the accuracy of the S-1011 Series A / C / E / G type is ±1.5%. It operates with current consumption of
600 nA typ.
Apart from the power supply pin, the detection voltage input pin (SENSE pin) is also prepared in the SENSE detection
product, so the output is stable even if the SENSE pin falls to 0 V.
The detection signal and release signal can be delayed by setting a capacitor externally, and the detection delay time
accuracy is ±20% (CN = 3.3 nF, Ta = +25°C), the release delay time accuracy is ±20% (CP = 3.3 nF, Ta = +25°C).
Output form is Nch open-drain output.
Features
Detection voltage:
Detection voltage accuracy:
Detection delay time accuracy:
Release delay time accuracy:
Current consumption:
Operation voltage range:
Hysteresis width:
Output form:
Operation temperature range:
Lead-free (Sn 100%), halogen-free
3.0 V to 10.0 V (0.05 V step) (SENSE detection product)
3.6 V to 10.0 V (0.05 V step) (VDD detection product)
±1.5% (A / C / E / G type)
±20% (CN = 3.3 nF)
±20% (CP = 3.3 nF)
600 nA typ.
1.8 V to 36.0 V
"Available" (5.0% typ.) / "unavailable" is selectable.
Nch open-drain output
Ta = 40°C to +85°C
Applications
Power supply monitor for microcomputer and reset for CPU
Constant voltage power supply monitor for TV and home appliance etc.
Power supply monitor for Blu-ray recorder, notebook PC and digital still camera
Industrial equipment, housing equipment
Package
SOT-23-6
Seiko Instruments Inc.
1


S-1011 Datasheet PDF
No Preview Available !

Click to Download PDF File for PC

HIGH-WITHSTAND VOLTAGE BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR
S-1011 Series
Rev.1.2_00
Block Diagrams
1. S-1011 Series A / J type (VDD detection product)
CP
VDD
*1
VREF
+
Delay
circuit
*1 *1
OUT
*1
Function
Voltage detection
Hysteresis width
Status
VDD detection
Available
(5.0% typ.)
VSS
*1. Parasitic diode
CN
Figure 1
2. S-1011 Series C / L type (VDD detection product)
CP
VDD
Function
Status
Voltage detection VDD detection
Hysteresis width Unavailable
VSS
*1
VREF
+
Delay
circuit
*1 *1
OUT
*1
*1. Parasitic diode
CN
Figure 2
2 Seiko Instruments Inc.


S-1011 Datasheet PDF
No Preview Available !

Click to Download PDF File for PC

HIGH-WITHSTAND VOLTAGE BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR
Rev.1.2_00
S-1011 Series
3. S-1011 Series E / N type (SENSE detection product)
SENSE
CP
VDD
+
*1 *1
Delay
circuit
Function
Voltage detection
Hysteresis width
Status
SENSE detection
Available
(5.0% typ.)
OUT
VREF
*1 *1
*1
VSS
CN
*1. Parasitic diode
Figure 3
4. S-1011 Series G / Q type (SENSE detection product)
SENSE
CP
VDD
Function
Status
Voltage detection SENSE detection
Hysteresis width Unavailable
VSS
+
*1 *1
VREF
Delay
circuit
*1 *1
OUT
*1
*1. Parasitic diode
CN
Figure 4
Seiko Instruments Inc.
3


S-1011 Datasheet PDF
No Preview Available !

Click to Download PDF File for PC

HIGH-WITHSTAND VOLTAGE BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR
S-1011 Series
Rev.1.2_00
Product Name Structure
Users can select the product type and detection voltage value for the S-1011 Series.
Refer to "1. Product name" regarding the contents of product name, "2. Function list of product types" regarding
the product types, "3. Package" regarding the package drawings and "4. Product name lists" regarding details of
the product name.
1. Product name
S-1011 x xx - M6T1 U 4
Environmental code
U: Lead-free (Sn 100%), halogen-free
Package abbreviation and IC packing specifications*1
M6T1: SOT-23-6, Tape
Detection voltage value
30 to A0
(e.g., when the output voltage is 3.0 V, it is expressed as 30.
when the output voltage is 10.0 V, it is expressed as A0.)
Product type*2
A, C, E, G, J, L, N, Q
*1. Refer to the tape drawing.
*2. Refer to "2. Function list of product types".
Remark
Although the detection voltage in the S-1011 Series is 10.0 V max., the detection voltage exceeding
10.0 V with an external resistor can be set.
Refer to "2. SENSE pin" in "Operation" for details.
2. Function list of product types
Product Type
A
C
E
G
J
L
N
Q
Voltage Detection
VDD detection
VDD detection
SENSE detection
SENSE detection
VDD detection
VDD detection
SENSE detection
SENSE detection
Table 1
Output Logic
Active "L"
Active "L"
Active "L"
Active "L"
Active "L"
Active "L"
Active "L"
Active "L"
Hysteresis Width
Available (5.0% typ.)
Unavailable
Available (5.0% typ.)
Unavailable
Available (5.0% typ.)
Unavailable
Available (5.0% typ.)
Unavailable
Detection Voltage
5.0 V to 10.0 V
5.0 V to 10.0 V
5.0 V to 10.0 V
5.0 V to 10.0 V
3.6 V to 4.95 V
3.6 V to 4.95 V
3.0 V to 4.95 V
3.0 V to 4.95 V
3. Package
Package Name
SOT-23-6
Table 2 Package Drawing Codes
Dimension
MP006-A-P-SD
Tape
MP006-A-C-SD
Reel
MP006-A-R-SD
4 Seiko Instruments Inc.


S-1011 Datasheet PDF
No Preview Available !

Click to Download PDF File for PC

HIGH-WITHSTAND VOLTAGE BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR
Rev.1.2_00
S-1011 Series
4. Product name lists
4. 1 S-1011 Series A type
Voltage detection: VDD detection
Hysteresis width: Available (5.0% typ.)
Output logic: Active "L"
Detection voltage: 5.0 V to 10.0 V
Table 3
Detection Voltage
SOT-23-6
5.0 V ± 1.5%
6.0 V ± 1.5%
7.0 V ± 1.5%
8.0 V ± 1.5%
9.0 V ± 1.5%
10.0 V ± 1.5%
S-1011A50-M6T1U4
S-1011A60-M6T1U4
S-1011A70-M6T1U4
S-1011A80-M6T1U4
S-1011A90-M6T1U4
S-1011AA0-M6T1U4
Remark Please contact our sales office for products with specifications other than the above.
4. 2 S-1011 Series C type
Voltage detection: VDD detection
Hysteresis width: Unavailable
Output logic: Active "L"
Detection voltage: 5.0 V to 10.0 V
Table 4
Detection Voltage
SOT-23-6
5.0 V ± 1.5%
6.0 V ± 1.5%
7.0 V ± 1.5%
8.0 V ± 1.5%
9.0 V ± 1.5%
10.0 V ± 1.5%
S-1011C50-M6T1U4
S-1011C60-M6T1U4
S-1011C70-M6T1U4
S-1011C80-M6T1U4
S-1011C90-M6T1U4
S-1011CA0-M6T1U4
Remark Please contact our sales office for products with specifications other than the above.
4. 3 S-1011 Series E type
Voltage detection: SENSE detection
Hysteresis width: Available (5.0% typ.)
Output logic: Active "L"
Detection voltage: 5.0 V to 10.0 V
Table 5
Detection Voltage
SOT-23-6
5.0 V ± 1.5%
6.0 V ± 1.5%
7.0 V ± 1.5%
8.0 V ± 1.5%
9.0 V ± 1.5%
10.0 V ± 1.5%
S-1011E50-M6T1U4
S-1011E60-M6T1U4
S-1011E70-M6T1U4
S-1011E80-M6T1U4
S-1011E90-M6T1U4
S-1011EA0-M6T1U4
Remark Please contact our sales office for products with specifications other than the above.
4. 4 S-1011 Series G type
Voltage detection: SENSE detection
Hysteresis width: Unavailable
Output logic: Active "L"
Detection voltage: 5.0 V to 10.0 V
Table 6
Detection Voltage
SOT-23-6
5.0 V ± 1.5%
6.0 V ± 1.5%
7.0 V ± 1.5%
8.0 V ± 1.5%
9.0 V ± 1.5%
10.0 V ± 1.5%
S-1011G50-M6T1U4
S-1011G60-M6T1U4
S-1011G70-M6T1U4
S-1011G80-M6T1U4
S-1011G90-M6T1U4
S-1011GA0-M6T1U4
Remark Please contact our sales office for products with specifications other than the above.
Seiko Instruments Inc.
5


S-1011 Datasheet PDF
No Preview Available !

Click to Download PDF File for PC

HIGH-WITHSTAND VOLTAGE BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR
S-1011 Series
Rev.1.2_00
4. 5 S-1011 Series J type
Voltage detection: VDD detection
Hysteresis width: Available (5.0% typ.)
Output logic: Active "L"
Detection voltage: 3.6 V to 4.95 V
Table 7
Detection Voltage
SOT-23-6
3.6 V ± 3.0%
4.2 V ± 2.5%
S-1011J36-M6T1U4
S-1011J42-M6T1U4
Remark Please contact our sales office for products with specifications other than the above.
4. 6 S-1011 Series L type
Voltage detection: VDD detection
Hysteresis width: Unavailable
Output logic: Active "L"
Detection voltage: 3.6 V to 4.95 V
Table 8
Detection Voltage
SOT-23-6
3.6 V ± 3.0%
4.2 V ± 2.5%
S-1011L36-M6T1U4
S-1011L42-M6T1U4
Remark Please contact our sales office for products with specifications other than the above.
4. 7 S-1011 Series N type
Voltage detection: SENSE detection
Hysteresis width: Available (5.0% typ.)
Output logic: Active "L"
Detection voltage: 3.0 V to 4.95 V
Table 9
Detection Voltage
SOT-23-6
3.0 V ± 3.0%
3.3 V ± 3.0%
3.6 V ± 3.0%
S-1011N30-M6T1U4
S-1011N33-M6T1U4
S-1011N36-M6T1U4
4.2 V ± 2.5%
S-1011N42-M6T1U4
Remark Please contact our sales office for products with specifications other than the above.
4. 8 S-1011 Series Q type
Voltage detection: SENSE detection
Hysteresis width: Unavailable
Output logic: Active "L"
Detection voltage: 3.0 V to 4.95 V
Table 10
Detection Voltage
SOT-23-6
3.0 V ± 3.0%
S-1011Q30-M6T1U4
3.3 V ± 3.0%
S-1011Q33-M6T1U4
3.6 V ± 3.0%
S-1011Q36-M6T1U4
4.2 V ± 2.5%
S-1011Q42-M6T1U4
Remark Please contact our sales office for products with specifications other than the above.
6 Seiko Instruments Inc.


S-1011 Datasheet PDF
No Preview Available !

Click to Download PDF File for PC

HIGH-WITHSTAND VOLTAGE BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR
Rev.1.2_00
S-1011 Series
Pin Configurations
1. S-1011 Series A / C / J / L type (VDD detection product)
1. 1 SOT-23-6
Top view
Table 11
654
123
Figure 5
Pin No.
Symbol
Description
1 VDD
2 NC*1
Voltage input pin
No connection
3 OUT
4 CP*2
Voltage detection output pin
Connection pin for release delay capacitor
5 VSS
6 CN*3
GND pin
Connection pin for detection delay capacitor
*1. The NC pin is electrically open.
The NC pin can be connected to the VDD pin or the VSS pin.
*2. Connect a capacitor between the CP pin and the VSS pin.
The release delay time can be adjusted according to the capacitance.
Moreover, the CP pin is available even when it is open.
*3. Connect a capacitor between the CN pin and the VSS pin.
The detection delay time can be adjusted according to the capacitance.
Moreover, the CN pin is available even when it is open.
2. S-1011 Series E / G / N / Q type (SENSE detection product)
2. 1 SOT-23-6
Top view
Table 12
654
123
Figure 6
Pin No.
Symbol
Description
1 VDD
Voltage input pin
2 SENSE Detection voltage input pin
3 OUT
4 CP*1
Voltage detection output pin
Connection pin for release delay capacitor
5 VSS
6 CN*2
GND pin
Connection pin for detection delay capacitor
*1. Connect a capacitor between the CP pin and the VSS pin.
The release delay time can be adjusted according to the capacitance.
Moreover, the CP pin is available even when it is open.
*2. Connect a capacitor between the CN pin and the VSS pin.
The detection delay time can be adjusted according to the capacitance.
Moreover, the CN pin is available even when it is open.
Seiko Instruments Inc.
7


S-1011 Datasheet PDF
No Preview Available !

Click to Download PDF File for PC

HIGH-WITHSTAND VOLTAGE BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR
S-1011 Series
Rev.1.2_00
Absolute Maximum Ratings
Table 13
(Ta = +25°C unless otherwise specified)
Item
Symbol
Absolute Maximum Rating
Unit
Power supply voltage
SENSE pin input voltage
CP pin input voltage
CN pin input voltage
Output voltage
Output current
Operation ambient temperature
Storage temperature
VDD VSS
VSENSE
VCP
VCN
VOUT
IOUT
Topr
Tstg
VSS 0.3 to VSS + 45
VSS 0.3 to VSS + 45
VSS 0.3 to VDD + 0.3 VSS + 7.0
VSS 0.3 to VDD + 0.3 VSS + 7.0
VSS 0.3 to VSS + 45
25
40 to +85
40 to +125
V
V
V
V
V
mA
°C
°C
Caution The absolute maximum ratings are rated values exceeding which the product could suffer
physical damage. These values must therefore not be exceeded under any conditions.
Thermal Resistance Value
Table 14
Item
Symbol
Condition
Junction-to-ambient thermal resistance*1 θja
SOT-23-6
Board 1
Board 2
*1. Test environment: compliance with JEDEC STANDARD JESD51-2A
Min. Typ. Max. Unit
159 °C/W
124 °C/W
Remark Refer to "Thermal Characteristics" for details of power dissipation and test board.
8 Seiko Instruments Inc.


S-1011 Datasheet PDF
No Preview Available !

Click to Download PDF File for PC

HIGH-WITHSTAND VOLTAGE BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR
Rev.1.2_00
S-1011 Series
Electrical Characteristics
1. VDD detection product
1. 1 S-1011 Series J / L type
Item Symbol
Table 15
Condition
(Ta = +25°C unless otherwise specified)
Min.
Typ.
Max.
Unit
Test
Circuit
Detection voltage*1 VDET
Hysteresis width
VHYS
Current consumption ISS
Operation voltage
VDD
Output current
IOUT
Leakage current
ILEAK
Detection delay time*4 tRESET
Release delay time*5 tDELAY
CP pin discharge
ON resistance
RCP
CN pin discharge
ON resistance
RCN
3.6 V ≤ −VDET(S) 4.15 V
4.2 V ≤ −VDET(S) 4.95 V
J type
3.6 V ≤ −VDET(S) 4.15 V
4.2 V ≤ −VDET(S) 4.95 V
L type*2
3.6 V ≤ −VDET(S) 4.95 V
VDD = VDET 0.1 V, 3.6 V ≤ −VDET 4.95 V
Output transistor
Nch
VDS*3 = 0.05 V
VDD = 2.9 V
Output transistor
Nch
VDD = 30.0 V, VOUT = 30.0 V
CN = 3.3 nF
CP = 3.3 nF
VDD = 6.9 V, VCP = 0.5 V
VDET(S)
× 0.970
VDET(S)
× 0.975
VDET
× 0.010
VDET
× 0.020
1.8
VDET(S)
VDET(S)
VDET
× 0.050
VDET
× 0.050
0
0.60
VDET(S)
× 1.030
VDET(S)
× 1.025
VDET
× 0.100
VDET
× 0.090
1.60
36.0
0.33
− − 2.0
8.0 10.0 12.0
8.0 10.0 12.0
0.52 2.2
V
V
V
V
V
μA
V
mA
μA
ms
ms
kΩ
VDD = 2.9 V, VCN = 0.5 V
1.0 5.0 kΩ
1
1
1
1
1
2
1
3
3
4
4
*1. VDET: Actual detection voltage value, VDET(S): Set detection voltage value
*2. Hysteresis width is "unavailable", so release voltage = detection voltage.
*3. VDS: Drain-to-source voltage of the output transistor
*4. The time period from when the pulse voltage of VDET(S) + 0.5 V → −VDET(S) 0.5 V is applied to the VDD pin to when
VOUT reaches VDD / 2, after the power supply voltage (VDD) reaches the release voltage once.
*5. The time period from when the pulse voltage of VDET(S) 0.5 V → −VDET(S) + 0.5 V is applied to the VDD pin to when
VOUT reaches VDD / 2.
Seiko Instruments Inc.
9


S-1011 Datasheet PDF
No Preview Available !

Click to Download PDF File for PC

HIGH-WITHSTAND VOLTAGE BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR
S-1011 Series
Rev.1.2_00
1. 2 S-1011 Series A / C type
Table 16
(Ta = +25°C unless otherwise specified)
Item Symbol
Condition
Min.
Typ.
Max.
Unit
Test
Circuit
Detection voltage*1
VDET 5.0 V ≤ −VDET(S) 10.0 V
VDET(S)
× 0.985
VDET(S)
VDET(S)
× 1.015
V
1
Hysteresis width
VHYS
A type
C type*2
VDET
× 0.030
VDET
× 0.050
0
VDET
× 0.080
V
V
1
1
Current consumption ISS
Operation voltage
VDD
VDD = VDET 0.1 V, 5.0 V ≤ −VDET 10.0 V
Output transistor
0.60 1.60 μA 2
1.8
36.0 V
1
Output current
IOUT
Leakage current
ILEAK
Detection delay time*4 tRESET
Release delay time*5 tDELAY
CP pin discharge
ON resistance
RCP
Nch
VDS*3 = 0.05 V
VDD = 4.5 V
Output transistor
Nch
VDD = 30.0 V, VOUT = 30.0 V
CN = 3.3 nF
CP = 3.3 nF
VDD = 14.0 V, VCP = 0.5 V
0.5
8.0
8.0
0.30
10.0
10.0
mA
2.0 μA
12.0 ms
12.0 ms
2.60 kΩ
3
3
4
4
CN pin discharge
ON resistance
RCN VDD = 4.5 V, VCN = 0.5 V
0.63
2.60 kΩ
*1. VDET: Actual detection voltage value, VDET(S): Set detection voltage value
*2. Hysteresis width is "unavailable", so release voltage = detection voltage.
*3. VDS: Drain-to-source voltage of the output transistor
*4. The time period from when the pulse voltage of VDET(S) + 1.0 V → −VDET(S) 1.0 V is applied to the VDD pin to when
VOUT reaches VDD / 2, after the power supply voltage (VDD) reaches the release voltage once.
*5. The time period from when the pulse voltage of VDET(S) 1.0 V → −VDET(S) + 1.0 V is applied to the VDD pin to when
VOUT reaches VDD / 2.
10 Seiko Instruments Inc.


S-1011 Datasheet PDF
No Preview Available !

Click to Download PDF File for PC

HIGH-WITHSTAND VOLTAGE BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR
Rev.1.2_00
S-1011 Series
2. SENSE detection product
2. 1 S-1011 Series N / Q type
Item Symbol
Table 17
Condition
(Ta = +25°C unless otherwise specified)
Min.
Typ.
Max.
Unit
Test
Circuit
Detection voltage*1
Hysteresis width
VDET
VHYS
3.0 V ≤ −VDET(S) 4.15 V
VDD = 16.0 V
4.2 V ≤ −VDET(S) 4.95 V
N type
VDD = 16.0 V
3.0 V ≤ −VDET(S) 4.15 V
4.2 V ≤ −VDET(S) 4.95 V
Q type*2 3.0 V ≤ −VDET(S) 4.95 V
VDET(S)
× 0.970
VDET(S)
× 0.975
VDET
× 0.010
VDET
× 0.020
VDET(S)
VDET(S)
VDET
× 0.050
VDET
× 0.050
VDET(S)
× 1.030
VDET(S)
× 1.025
VDET
× 0.100
VDET
× 0.090
0
V
V
V
V
V
1
1
1
1
1
Current
consumption*3
Operation voltage
Output current
ISS
VDD
IOUT
Leakage current
ILEAK
Detection delay time*5 tRESET
Release delay time*6 tDELAY
SENSE pin resistance RSENSE
CP pin discharge
ON resistance
RCP
CN pin discharge
ON resistance
RCN
VDD = 16.0 V, VSENSE = VDET 0.1 V,
3.0 V ≤ −VDET 4.95 V
Output transistor
Nch
VDS*4 = 0.05 V
VDD = 5.0 V, VSENSE = 2.9 V
Output transistor VDD = 30.0 V, VOUT = 30.0 V,
Nch
VSENSE = 30.0 V
CN = 3.3 nF
CP = 3.3 nF
VDD = 3.0 V, VSENSE = 6.9 V, VCP = 0.5 V
VDD = 3.0 V, VSENSE = 2.9 V, VCN = 0.5 V
3.0
0.5
8.0
8.0
6.8
0.72
0.72
0.55 1.55 μA 2
36.0 V
1
− − mA 3
2.0 μA 3
10.0 12.0 ms 4
10.0 12.0 ms 4
275 MΩ 2
4.29 kΩ −
4.29 kΩ −
*1. VDET: Actual detection voltage value, VDET(S): Set detection voltage value
*2. Hysteresis width is "unavailable", so release voltage = detection voltage.
*3. The current flowing through the SENSE pin resistance is not included.
*4. VDS: Drain-to-source voltage of the output transistor
*5. The time period from when the pulse voltage of VDET(S) + 0.5 V → −VDET(S) 0.5 V is applied to the SENSE pin to
when VOUT reaches VDD / 2, after voltage of 16.0 V is applied to the VDD pin and the SENSE pin input voltage (VSENSE)
reaches the release voltage once.
*6. The time period from when voltage of 16.0 V is applied to the VDD pin and the pulse voltage of VDET(S) 0.5 V
VDET(S) + 0.5 V is applied to the SENSE pin to when VOUT reaches VDD / 2.
Seiko Instruments Inc.
11


S-1011 Datasheet PDF
No Preview Available !

Click to Download PDF File for PC

HIGH-WITHSTAND VOLTAGE BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR
S-1011 Series
Rev.1.2_00
2. 2 S-1011 Series E / G type
Table 18
Item
Detection voltage*1
Hysteresis width
Symbol
Condition
VDET VDD = 16.0 V, 5.0 V ≤ −VDET(S) 10.0 V
VHYS
VDD = 16.0 V
E type
G type*2
(Ta = +25°C unless otherwise specified)
Min.
Typ.
Max.
Unit
Test
Circuit
VDET(S)
× 0.985
VDET(S)
VDET(S)
× 1.015
V
1
VDET VDET VDET
× 0.030 × 0.050 × 0.080
V
1
0 V1
Current
consumption*3
ISS
VDD = 16.0 V, VSENSE = VDET 0.1 V,
5.0 V ≤ −VDET 10.0 V
Operation voltage
VDD
Output transistor
0.55 1.55 μA
2
3.0
36.0 V
1
Output current
IOUT
Leakage current
ILEAK
Detection delay time*5 tRESET
Release delay time*6 tDELAY
SENSE pin resistance RSENSE
CP pin discharge
ON resistance
RCP
Nch
VDS*4 = 0.05 V
VDD = 5.0 V, VSENSE = 4.5 V
Output transistor VDD = 30.0 V, VOUT = 30.0 V,
Nch
VSENSE = 30.0 V
CN = 3.3 nF
CP = 3.3 nF
VDD = 4.5 V, VSENSE = 14.0 V, VCP = 0.5 V
0.5
8.0
8.0
26.0
0.30
10.0
10.0
mA
2.0 μA
12.0 ms
12.0 ms
400 MΩ
2.60 kΩ
3
3
4
4
2
CN pin discharge
ON resistance
RCN VDD = 4.5 V, VSENSE = 4.5 V, VCN = 0.5 V
0.63
2.60 kΩ
*1. VDET: Actual detection voltage value, VDET(S): Set detection voltage value
*2. Hysteresis width is "unavailable", so release voltage = detection voltage.
*3. The current flowing through the SENSE pin resistance is not included.
*4. VDS: Drain-to-source voltage of the output transistor
*5. The time period from when the pulse voltage of VDET(S) + 1.0 V → −VDET(S) 1.0 V is applied to the SENSE pin to
when VOUT reaches VDD / 2, after voltage of 16.0 V is applied to the VDD pin and the SENSE pin input voltage (VSENSE)
reaches the release voltage once.
*6. The time period from when voltage of 16.0 V is applied to the VDD pin and the pulse voltage of VDET(S) 1.0 V
VDET(S) + 1.0 V is applied to the SENSE pin to when VOUT reaches VDD / 2.
12 Seiko Instruments Inc.


S-1011 Datasheet PDF
No Preview Available !

Click to Download PDF File for PC

HIGH-WITHSTAND VOLTAGE BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR
Rev.1.2_00
S-1011 Series
Test Circuits
VDD
R
100 kΩ
VDD
R
100 kΩ
VDD OUT
+
V
VSS CP CN
+
V
VDD
VSENSE
SENSE
OUT
+
V
VSS CP
CN
+
V
+A
VDD
Figure 7 Test Circuit 1
(VDD detection product)
VDD
OUT
VSS CP CN
Figure 8 Test Circuit 1
(SENSE detection product)
+A
VDD
+
VSENSE
A
VDD
SENSE
OUT
VSS CP CN
Figure 9 Test Circuit 2
(VDD detection product)
Figure 10 Test Circuit 2
(SENSE detection product)
VDD
VDD
++
VDD
OUT
+ VSS CP CN
V
A
+
VDS
VDD
+ VSENSE
V
SENSE
OUT
VSS CP CN
A
+
VDS
VV
Figure 11 Test Circuit 3
(VDD detection product)
Figure 12 Test Circuit 3
(SENSE detection product)
P.G. +
VDD
OUT
VSS CP CN
R
100 kΩ
Oscilloscope
VDD P.G. +
VDD
SENSE
OUT
VSS CP CN
R
100 kΩ
Oscilloscope
Figure 13 Test Circuit 4
(VDD detection product)
Figure 14 Test Circuit 4
(SENSE detection product)
Seiko Instruments Inc.
13


S-1011 Datasheet PDF
No Preview Available !

Click to Download PDF File for PC

HIGH-WITHSTAND VOLTAGE BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR
S-1011 Series
Rev.1.2_00
Standard Circuits
1. VDD detection product
VDD
OUT
R
100 kΩ
VSS
CP CN
CP*1
CN*2
*1. The delay capacitor (CP) should be connected directly to the CP pin and the VSS pin.
*2. The delay capacitor (CN) should be connected directly to the CN pin and the VSS pin.
Figure 15
2. SENSE detection product
VDD
SENSE
OUT
R
100 kΩ
VSS
CP CN
CP*1
CN*2
*1. The delay capacitor (CP) should be connected directly to the CP pin and the VSS pin.
*2. The delay capacitor (CN) should be connected directly to the CN pin and the VSS pin.
Figure 16
Caution The above connection diagram and constant will not guarantee successful operation.
Perform thorough evaluation using the actual application to set the constant.
14 Seiko Instruments Inc.


S-1011 Datasheet PDF
No Preview Available !

Click to Download PDF File for PC

HIGH-WITHSTAND VOLTAGE BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR
Rev.1.2_00
S-1011 Series
Explanation of Terms
1. Detection voltage (VDET)
The detection voltage is a voltage at which the output in Figure 21 or Figure 22 turns to "L" (VDD detection
product: VDD, SENSE detection product: VSENSE). The detection voltage varies slightly among products of the same
specification. The variation of detection voltage between the specified minimum (VDET min.) and the maximum
(VDET max.) is called the detection voltage range (Refer to Figure 17, Figure 19).
Example: In VDET = 5.0 V product, the detection voltage is either one in the range of 4.925 V ≤ −VDET 5.075 V.
This means that some VDET = 5.0 V product have VDET = 4.925 V and some have VDET = 5.075 V.
2. Release voltage (+VDET)
The release voltage is a voltage at which the output in Figure 21 or Figure 22 turns to "H" (VDD detection product:
VDD, SENSE detection product: VSENSE).
The difference of detection voltage and release voltage is 5.0% typ.
The release voltage varies slightly among products of the same specification. The variation of release voltage
between the specified minimum (+VDET min.) and the maximum (+VDET max.) is called the release voltage range
(Refer to Figure 18, Figure 20). The range is calculated from the actual detection voltage (VDET) of a product.
In the S-1011 Series C / G / L / Q type, the release voltage (+VDET) is the same value as the actual detection
voltage (VDET) of a product.
Example: In VDET = 6.0 V product, the release voltage is either one in the range of 6.0873 V ≤ +VDET 6.5772 V.
This means that some VDET = 6.0 V product have +VDET = 6.0873 V and some have +VDET = 6.5772 V.
Seiko Instruments Inc.
15


S-1011 Datasheet PDF
No Preview Available !

Click to Download PDF File for PC

HIGH-WITHSTAND VOLTAGE BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR
S-1011 Series
Rev.1.2_00
VDD
VDET max.
VDET min.
Detection voltage Release voltage
Detection voltage
range
+VDET max.
+VDET min.
VDD
Release voltage
range
VOUT
tRESET
Figure 17 Detection Voltage (VDD detection product)
VOUT
tDELAY
Figure 18 Release Voltage (VDD detection product)
VSENSE
Detection voltage Release voltage
VDET max.
VDET min.
Detection voltage
range
+VDET max.
+VDET min.
VSENSE
Release voltage
range
VOUT
tRESET
Figure 19 Detection Voltage
(SENSE detection product)
VOUT
tDELAY
Figure 20 Release Voltage
(SENSE detection product)
VDD
R
100 kΩ
VDD
R
100 kΩ
VDD
OUT
VDD
SENSE
OUT
+
V
VSS CP CN
+
V
VSENSE
+
V
VSS CP
CN
+
V
Figure 21 Test Circuit of Detection Voltage
and Release Voltage
(VDD detection product)
Figure 22 Test Circuit of Detection Voltage
and Release Voltage
(SENSE detection product)
3. Hysteresis width (VHYS)
The hysteresis width is the voltage difference between the detection voltage and the release voltage (the voltage at
point B the voltage at point A = VHYS in Figure 24 and Figure 28). Setting the hysteresis width between the
detection voltage and the release voltage, prevents malfunction caused by noise on the input voltage.
4. Feed-through current
The feed-through current is a current that flows instantaneously to the VDD pin at the time of detection and release
of a voltage detector.
16 Seiko Instruments Inc.


S-1011 Datasheet PDF
No Preview Available !

Click to Download PDF File for PC

HIGH-WITHSTAND VOLTAGE BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR
Rev.1.2_00
S-1011 Series
Operation
1. Basic operation
1. 1 S-1011 Series A / J type
(1) When the power supply voltage (VDD) is the release voltage (+VDET) or higher, the Nch transistor is turned off to
output VDD ("H") when the output is pulled up.
Since the Nch transistor (N1) is turned off, the input voltage to the comparator is
(RB + RC ) VDD
RA + RB + RC
.
(2) Even if VDD decreases to +VDET or lower, VDD is output when VDD is higher than the detection voltage (VDET).
When VDD decreases to VDET or lower (point A in Figure 24), the Nch transistor is turned on. And then VSS ("L")
is output from the OUT pin after the elapse of the detection delay time (tRESET).
At this time, N1 is turned on, and the input voltage to the comparator is
RB VDD
RA + RB
.
(3) The output is unstable when VDD decreases to the IC's minimum operation voltage or lower. VDD is output when
the output is pulled up.
(4) VSS is output by increasing VDD to the minimum operation voltage or higher. Even if VDD exceeds VDET, VSS is
output when VDD is lower than +VDET.
(5) When VDD increases to +VDET or higher (point B in Figure 24), the Nch transistor is turned off. And then VDD is
output from the OUT pin after the elapse of the release delay time (tDELAY) when the output is pulled up.
VDD
VDD
VSS
RA
*1
VREF
RB
RC
+
N1
Delay
circuit
Nch
*1 *1
OUT
R
100 kΩ
*1
+
V
CP CN
CP CN
*1. Parasitic diode
Figure 23 Operation of S-1011 Series A / J Type
(1) (2) (3) (4) (5)
Hysteresis width
(VHYS)
VDD
A
B Release voltage (+VDET)
Detection voltage (VDET)
Minimum operation voltage
VSS
VDD
Output from OUT pin
VSS
Remark
tRESET
tDELAY
When VDD is the minimum operation voltage or lower, the output voltage from the OUT pin is unstable in
the shaded area.
Figure 24 Timing Chart of S-1011 Series A / J Type
Seiko Instruments Inc.
17


S-1011 Datasheet PDF
No Preview Available !

Click to Download PDF File for PC

HIGH-WITHSTAND VOLTAGE BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR
S-1011 Series
Rev.1.2_00
1. 2 S-1011 Series C / L type
(1) When the power supply voltage (VDD) is the release voltage (+VDET) or higher, the Nch transistor is turned off to
output VDD ("H") when the output is pulled up.
At this time, the input voltage to the comparator is
(RB + RC ) VDD
RA + RB + RC
.
(2) When VDD decreases to the detection voltage (VDET) or lower (point A in Figure 26), the Nch transistor is
turned on. And then VSS ("L") is output from the OUT pin after the elapse of the detection delay time (tRESET).
(3) The output is unstable when VDD decreases to the IC's minimum operation voltage or lower. VDD is output when
the output is pulled up.
(4) VSS is output by increasing VDD to the minimum operation voltage or higher.
(5) When VDD increases to +VDET or higher (point B in Figure 26), the Nch transistor is turned off. And then VDD is
output from the OUT pin after the elapse of the release delay time (tDELAY) when the output is pulled up.
VDD
VDD
VSS
RA
*1
VREF
RB
RC
+
Delay
circuit
Nch
*1 *1
OUT
R
100 kΩ
*1
+
V
CP CN
CP CN
*1. Parasitic diode
Figure 25 Operation of S-1011 Series C / L Type
(1) (2) (3) (4) (5)
Detection voltage (VDET)
VDD
A
Output from OUT pin
B Release voltage (+VDET)
Minimum operation voltage
VSS
VDD
VSS
Remark 1.
2.
tRESET
tDELAY
When VDD is the minimum operation voltage or lower, the output voltage from the OUT pin is unstable
in the shaded area.
The release voltage is set to the same value as the detection voltage, since there is no hysteresis
width.
Figure 26 Timing Chart of S-1011 Series C / L Type
18 Seiko Instruments Inc.


S-1011 Datasheet PDF
No Preview Available !

Click to Download PDF File for PC

HIGH-WITHSTAND VOLTAGE BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR
Rev.1.2_00
S-1011 Series
1. 3 S-1011 Series E / N type
(1) When the power supply voltage (VDD) is the minimum operation voltage or higher, and the SENSE pin voltage
(VSENSE) is the release voltage (+VDET) or higher, the Nch transistor is turned off to output VDD ("H") when the
output is pulled up.
Since the Nch transistor (N1) is turned off, the input voltage to the comparator is
(RB +
RA
RC ) VSENSE
+ RB + RC
.
(2) Even if VSENSE decreases to +VDET or lower, VDD is output when VSENSE is higher than the detection voltage
(VDET).
When VSENSE decreases to VDET or lower (point A in Figure 28), the Nch transistor is turned on. And then VSS
("L") is output from the OUT pin after the elapse of the detection delay time (tRESET).
At this time, N1 is turned on, and the input voltage to the comparator is
RB
RA
VSENSE
+ RB
.
(3) Even if VSENSE further decreases to the IC's minimum operation voltage or lower, the output from the OUT pin is
stable when VDD is minimum operation voltage or higher.
(4) Even if VSENSE exceeds VDET, VSS is output when VSENSE is lower than +VDET.
(5) When VSENSE increases to +VDET or higher (point B in Figure 28), the Nch transistor is turned off. And then VDD
is output from the OUT pin after the elapse of the release delay time (tDELAY) when the output is pulled up.
VDD
VDD
VSENSE
VSS
SENSE
RA
*1 *1
VREF
RB
RC
+
N1
Delay
circuit
Nch
*1 *1
OUT
R
100 kΩ
*1
+
V
CP CN
CP CN
*1. Parasitic diode
Figure 27 Operation of S-1011 Series E / N Type
(1) (2) (3) (4) (5)
Hysteresis width
(VHYS)
VSENSE
A
B Release voltage (+VDET)
Detection voltage (VDET)
Minimum operation voltage
VSS
Output from OUT pin
VDD
VSS
tRESET
tDELAY
Figure 28 Timing Chart of S-1011 Series E / N Type
Seiko Instruments Inc.
19


S-1011 Datasheet PDF
No Preview Available !

Click to Download PDF File for PC

HIGH-WITHSTAND VOLTAGE BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR
S-1011 Series
Rev.1.2_00
1. 4 S-1011 Series G / Q type
(1) When the power supply voltage (VDD) is the minimum operation voltage or higher, and the SENSE pin voltage
(VSENSE) is the release voltage (+VDET) or higher, the Nch transistor is turned off to output VDD ("H") when the
output is pulled up.
At this time, the input voltage to the comparator is
(RB +
RA
RC ) VSENSE
+ RB + RC
.
(2) When VSENSE decreases to the detection voltage (VDET) or lower (point A in Figure 30), the Nch transistor is
turned on. And then VSS ("L") is output from the OUT pin after the elapse of the detection delay time (tRESET).
(3) Even if VSENSE further decreases to the IC's minimum operation voltage or lower, the output from the OUT pin is
stable when VDD is minimum operation voltage or higher.
(4) Even if VSENSE increases, VSS is output when VSENSE is lower than +VDET.
(5) When VSENSE increases to +VDET or higher (point B in Figure 30), the Nch transistor is turned off. And then VDD
is output from the OUT pin after the elapse of the release delay time (tDELAY) when the output is pulled up.
VDD
VDD
VSENSE
VSS
SENSE
RA
*1 *1
VREF
RB
RC
+
Delay
circuit
Nch
*1 *1
OUT
R
100 kΩ
*1
+
V
CP CN
CP CN
*1. Parasitic diode
Figure 29 Operation of S-1011 Series G / Q Type
(1) (2) (3) (4) (5)
Detection voltage (VDET)
VSENSE
A
B Release voltage (+VDET)
Minimum operation voltage
VSS
Output from OUT pin
VDD
VSS
tRESET
tDELAY
Remark The release voltage is set to the same value as the detection voltage, since there is no hysteresis width.
Figure 30 Timing Chart of S-1011 Series G / Q Type
20 Seiko Instruments Inc.


S-1011 Datasheet PDF
No Preview Available !

Click to Download PDF File for PC

HIGH-WITHSTAND VOLTAGE BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR
Rev.1.2_00
S-1011 Series
2. SENSE pin
2. 1 Error when detection voltage is set externally
The detection voltage for the S-1011 Series is 10.0 V max., however, in the SENSE detection product with VDET =
10.0 V, the detection voltage can be set externally by connecting a node that was resistance-divided by the resistor
(RA) and the resistor (RB) to the SENSE pin as shown in Figure 31.
For conventional products without the SENSE pin, external resistor cannot be too large since the resistance-divided
node must be connected to the VDD pin. This is because a feed-through current will flow through the VDD pin
when it goes from detection to release, and if external resistor is large, problems such as oscillation or larger error
in the hysteresis width may occur.
In the S-1011 Series, RA and RB in Figure 31 are easily made larger since the resistance-divided node can be
connected to the SENSE pin through which no feed-through current flows. However, be careful of error in the
current flowing through the internal resistance (RSENSE) that will occur.
Although RSENSE in the S-1011 Series is large (the S-1011 Series E / G type: 26 MΩ min., the S-1011 Series N / Q
type: 6.8 MΩ min.) to make the error small, RA and RB should be selected such that the error is within the allowable
limits.
2. 2 Selection of RA and RB
In Figure 31, the relation between the external setting detection voltage (VDX) and the actual detection voltage
(VDET) is ideally calculated by the equation below.
( )VDX = VDET ×
1+
RA
RB
··· (1)
However, in reality there is an error in the current flowing through RSENSE.
When considering this error, the relation between VDX and VDET is calculated as follows.
(VDX = VDET × 1 +
= VDET × 1 +
(= VDET × 1 +
)RA
RB || RSENSE
RA
RB × RSENSE
RB + RSENSE
)RA
RB
+
RA
RSENSE
× −VDET
··· (2)
By using equations (1) and (2), the error is calculated as VDET ×
RA
RSENSE
.
The error rate is calculated as follows by dividing the error by the right-hand side of equation (1).
RA × RB
RSENSE × (RA + RB)
× 100 [%] =
RA || RB
RSENSE
× 100 [%]
··· (3)
As seen in equation (3), the smaller the resistance values of RA and RB compared to RSENSE, the smaller the error
rate becomes.
Seiko Instruments Inc.
21


S-1011 Datasheet PDF
No Preview Available !

Click to Download PDF File for PC

HIGH-WITHSTAND VOLTAGE BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR
S-1011 Series
Rev.1.2_00
Also, the relation between the external setting hysteresis width (VHX) and the hysteresis width (VHYS) is calculated
by equation below. Error due to RSENSE also occurs to the relation in a similar way to the detection voltage.
( )VHX = VHYS ×
1+
RA
RB
··· (4)
A
VDX
RA
VDET
RB
VDD
SENSE
RSENSE
VSS
OUT
Figure 31 Detection Voltage External Setting Circuit
Caution 1. When externally setting the detection voltage, perform the operation with VDET = 10.0 V product.
Contact our sales office for details.
2. If the current flowing through RB is set to 1 μA or less, the error may become larger.
3. If the parasitic resistance and parasitic inductance between VDX point A and point A VDD pin
are larger, oscillation may occur. Perform thorough evaluation using the actual application.
4. If RA and RB are large, the SENSE pin input impedance becomes higher and may cause a
malfunction due to noise. In this case, connect a capacitor between the SENSE pin and the VSS
pin.
22 Seiko Instruments Inc.


S-1011 Datasheet PDF
No Preview Available !

Click to Download PDF File for PC

HIGH-WITHSTAND VOLTAGE BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR
Rev.1.2_00
S-1011 Series
3. Delay circuit
The delay circuit has a function that adjusts the detection delay time (tRESET) from when the power supply voltage
(VDD) or SENSE pin voltage (VSENSE) reaches the detection voltage (VDET) or lower to when the output from OUT
pin inverts.
It also has a function that adjusts the release delay time (tDELAY) from when the power supply voltage (VDD) or
SENSE pin voltage (VSENSE) reaches the release voltage (+VDET) to when the output from OUT pin inverts.
tRESET is determined by the delay coefficient, the delay capacitor (CN) and the detection delay time when the CN pin
is open (tRESET0), and the tDELAY is determined by the delay coefficient, the delay capacitor (CP) and the release
delay time when the CP pin is open (tDELAY0). They are calculated by the equation below.
tRESET [ms] = Delay coefficient × CN [nF] + tRESET0 [ms]
tDELAY [ms] = Delay coefficient × CP [nF] + tDELAY0 [ms]
Operation
Temperature
Ta = +85°C
Ta = +25°C
Ta = 40°C
Min.
2.41
2.41
2.40
Table 19
Delay Coefficient
Typ.
2.85
2.86
2.83
Max.
3.32
3.30
3.25
Operation
Temperature
Ta = 40°C to +85°C
Table 20
Detection Delay Time
when CN Pin is Open (tRESET0)
Typ.
0.35 ms
Release Delay Time
when CP Pin is Open (tDELAY0)
Typ.
0.35 ms
Caution 1.
2.
3.
Mounted board layout should be made in such a way that no current flows into or flows from
the CN pin or CP pin since the impedance of the CN pin and CP pin are high, otherwise correct
delay time cannot be provided.
There is no limit for the capacitance of CN and CP as long as the leakage current of the
capacitor can be ignored against the built-in constant current value (approximately 300 nA).
The leakage current may cause error in delay time. When the leakage current is larger than the
built-in constant current, no detect or release takes place.
The above equation will not guarantee successful operation. Determine the capacitance of CN
and CP through thorough evaluation including temperature characteristics in the actual usage
conditions.
When using an X8R equivalent capacitor, refer to the "2. Detection delay time (tRESET) vs.
Temperature (Ta)", "3. Detection delay time (tRESET) vs. Power supply voltage (VDD)", "5.
Release delay time (tDELAY) vs. Temperature (Ta)" and "6. Release delay time (tDELAY) vs.
Power supply voltage (VDD)" in "Reference Data" for details.
Seiko Instruments Inc.
23


S-1011 Datasheet PDF
No Preview Available !

Click to Download PDF File for PC

HIGH-WITHSTAND VOLTAGE BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR
S-1011 Series
Rev.1.2_00
Usage Precautions
1. Feed-through current during detection and release
In the S-1011 Series, the feed-through current flows at the time of detection and release. For this reason, if the
input impedance is high, oscillation may occur due to voltage drop caused by the feed-through current.
When using the S-1011 Series in configurations like those shown in Figure 32 and Figure 33, it is recommended
that input impedance be set to 1 kΩ or less.
Determine the impedance through thorough evaluation including temperature characteristics.
RA
VBAT
VDD
VDD
OUT
VSS CP CN
VBAT
RA VDD
VDD
SENSE
OUT
VSS CP CN
Figure 32 VDD Detection Product
Figure 33 SENSE Detection Product
24 Seiko Instruments Inc.


S-1011 Datasheet PDF
No Preview Available !

Click to Download PDF File for PC

HIGH-WITHSTAND VOLTAGE BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR
Rev.1.2_00
S-1011 Series
2. Power on and shut down sequence
SENSE detection products monitor SENSE pin voltage (VSENSE) while power is being supplied to the VDD pin.
Apply power in the order, the VDD pin then the SENSE pin.
In addition, when shutting down VDD pin, shut down the SENSE pin first, and shut down the VDD pin after the
detection delay time (tRESET) has elapsed.
VDD
VSENSE
VOUT
VDET
tDELAY
VDET(S)
tRESET
Figure 34
3. Falling power (reference)
Figure 35 shows the relation between VDD amplitude (VP-P) and input voltage falling time (tF) where the release
status can be maintained when the VDD pin (VDD detection product) sharply drops to a voltage equal to or higher
than the detection voltage (VDET) during release status.
S-1011A50
40.0
Ta = 40°C to +85°C
30.0
20.0
10.0
0.0
0.1
1
tF [s]
Figure 35
10
VIH*1
VDET
tF
VP-P
VDD VIL*2
VDET
VSS
*1. VIH = 36.0 V
*2. VIL = VDET(S) + 1.0 V
Figure 36 VDD Pin Input Voltage Waveform
Caution
Figure 35 shows the input voltage conditions which can maintain the release status. If the
voltage whose VP-P and tF are larger than these conditions is input to the VDD pin (VDD detection
product), the OUT pin may change to a detection status.
Seiko Instruments Inc.
25


S-1011 Datasheet PDF
No Preview Available !

Click to Download PDF File for PC

HIGH-WITHSTAND VOLTAGE BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR
S-1011 Series
Rev.1.2_00
4. Detection delay time accuracy (reference)
Figure 37 and Figure 38 show the relation between VDD amplitude (VP-P) and input voltage falling time (tF) where
the arbitrarily set detection delay time accuracy can be maintained when the VDD pin (VDD detection product)
sharply drops.
S-1011A50
40.0
30.0
20.0
10.0
0.0
0.1
Ta = 40°C to +85°C
1
tF [s]
10
S-1011A50
40.0
30.0
20.0
10.0
0.0
0.1
Ta = 40°C to +85°C
1
tF [s]
10
Figure 37 CN = 3.3 nF
Figure 38 CN = 100 nF
VIH*1
VDET
VDD
VDET
VIL*2
3.0 V
VSS
tF
VP-P
*1. VIH = 36.0 V
*2. VIL = VDET(S) 1.0 V (3.0 V min.)
Figure 39 VDD Pin Input Voltage Waveform
Caution
Figure 37 and Figure 38 show the input voltage conditions which can maintain the detection
delay time accuracy. If the voltage whose VP-P and tF are larger than these conditions is input to
the VDD pin (VDD detection product), the desired detection delay time may not be achieved.
26 Seiko Instruments Inc.


S-1011 Datasheet PDF
No Preview Available !

Click to Download PDF File for PC

HIGH-WITHSTAND VOLTAGE BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR
Rev.1.2_00
S-1011 Series
5. VDD drop during release delay time (reference)
Figure 40 and Figure 41 show the relation between pulse width (tPW) and VDD lower limit (VDROP) where a release
signal can be output after the normal release delay time has elapsed when the VDD pin (VDD detection product)
instantaneously drops to the detection voltage (VDET) or lower and then increases to the release voltage (+VDET) or
higher during release delay time.
S-1011A50
Ta = 40°C to +85°C, CP = CN = 3.3 nF,
10000
1000
100 Inhibited Area
10
1
0.0
0.5 1.0 1.5
VDROP [V]
2.0
S-1011AA0
Ta = 40°C to +85°C, CP = CN = 3.3 nF,
10000
1000
100 Inhibited Area
10
1
0.0
0.5 1.0 1.5
VDROP [V]
2.0
Figure 40
Figure 41
16 V
tF*1 tPW
tR*1
VDD VDET
VDROP
tDELAY 0.8
tDELAY
VOUT
*1. tR = tF = 10 μs
Figure 42 VDD Pin Input Voltage Waveform
Caution 1.
2.
Figure 40 and Figure 41 show the input voltage conditions when a release signal is output
after the normal release delay time has elapsed. When this is within the inhibited area, release
may erroneously be executed before the delay time completes.
When the VDD pin voltage is within the inhibited areas shown in Figure 40 and Figure 41
during release delay time, input 0 V to the VDD pin then restart the S-1011 Series.
Seiko Instruments Inc.
27


S-1011 Datasheet PDF
No Preview Available !

Click to Download PDF File for PC

HIGH-WITHSTAND VOLTAGE BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR
S-1011 Series
Rev.1.2_00
Precautions
Do not apply an electrostatic discharge to this IC that exceeds the performance ratings of the built-in electrostatic
protection circuit.
Because the SENSE pin has a high impedance, malfunctions may occur due to noise.
Be careful of wiring adjoining SENSE pin wiring in actual applications.
When designing for mass production using an application circuit described herein, the product deviation and
temperature characteristics of the external parts should be taken into consideration. SII shall not bear any
responsibility for patent infringements related to products using the circuits described herein.
SII claims no responsibility for any disputes arising out of or in connection with any infringement by products
including this IC of patents owned by a third party.
28 Seiko Instruments Inc.


S-1011 Datasheet PDF
No Preview Available !

Click to Download PDF File for PC

HIGH-WITHSTAND VOLTAGE BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR
Rev.1.2_00
S-1011 Series
Characteristics (Typical Data)
1. Detection voltage (VDET), Release voltage (+VDET) vs. Temperature (Ta)
1. 1 VDD detection product
1. 2 SENSE detection product
S-1011A50
S-1011E50
5.40 5.40
5.30
VDET
5.30
VDET
VDD = 16.0 V
5.20 5.20
5.10
5.00
VDET
5.10
5.00
VDET
4.90
40 25
0 25 50
Ta [C]
75 85
4.90
40 25
0 25 50
Ta [C]
75 85
2. Detection voltage (VDET), Release voltage (+VDET) vs. Power supply voltage (VDD)
2. 1 SENSE detection product
S-1011E50
5.40
5.30 VDET
5.20 Ta = 25C
5.10
Ta = 40C
Ta = 85C
5.00
4.90 VDET
0.0 6.0
12.0 18.0 24.0 30.0 36.0
VDD [V]
3. Current consumption (ISS) vs. Power supply voltage (VDD)
3. 1 VDD detection product
S-1011A50
1.50
VDD = 0 V 36.0 V
Ta = +85°C
1.00
0.50 Ta = +25°C
Ta = 40°C
0.00
0.0 6.0 12.0 18.0 24.0 30.0 36.0
VDD [V]
3. 2 SENSE detection product
S-1011E50
VDD = 0 V 36.0 V,
VSENSE = VDET 0.1 V (during detection)
1.50
Ta = 40°C
Ta = +25°C
1.00
0.50
0.00
0.0
Ta = +85°C
6.0 12.0 18.0 24.0 30.0 36.0
VDD [V]
S-1011E50
VDD = 0 V 36.0 V,
VSENSE = +VDET + 0.1 V (during release)
1.50
1.00
Ta = 40°C
Ta = +25°C
0.50
0.00
0.0
Ta = +85°C
6.0 12.0 18.0 24.0 30.0 36.0
VDD [V]
Seiko Instruments Inc.
29


S-1011 Datasheet PDF
No Preview Available !

Click to Download PDF File for PC

HIGH-WITHSTAND VOLTAGE BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR
S-1011 Series
Rev.1.2_00
4. Current consumption (ISS) vs. Temperature (Ta)
4. 1 VDD detection product
4. 2 SENSE detection product
S-1011A50
1.50
VDD = +VDET + 0.1 V
S-1011E50
1.50
VDD = 16.0 V, VSENSE = +VDET + 0.1 V
1.00 1.00
0.50 0.50
0.00
40 25
0 25 50
Ta [C]
75 85
0.00
40 25
0 25 50
Ta [C]
75 85
5. Current consumption during detection delay (ISS) vs. Temperature (Ta)
5. 1 VDD detection product
5. 2 SENSE detection product
S-1011A50
3.00
VCN = 0.2 V
S-1011E50
3.00
VDD = 16.0 V, VCN = 0.2 V
2.00 2.00
1.00 1.00
0.00
40 25
0 25 50
Ta [C]
75 85
0.00
40 25
0 25 50
Ta [C]
75 85
6. Current consumption during release delay (ISS) vs. Temperature (Ta)
6. 1 VDD detection product
6. 2 SENSE detection product
S-1011A50
3.00
VCP = 0.2 V
S-1011E50
3.00
VDD = 16.0 V, VCP = 0.2 V
2.00 2.00
1.00 1.00
0.00
40 25
0 25 50
Ta [C]
75 85
0.00
40 25
0 25 50
Ta [C]
75 85
30 Seiko Instruments Inc.




Click to Download PDF File for PC





HOME