Seiko Instruments Electronic Components Datasheet


S-1004

VOLTAGE DETECTOR


S-1004 Datasheet PDF
No Preview Available !

Click to Download PDF File for PC

S-1004 Series
www.sii-ic.com
© Seiko Instruments Inc., 2014
BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING)
VOLTAGE DETECTOR WITH SENSE PIN
Rev.2.1_00
The S-1004 Series is a high-accuracy voltage detector developed using CMOS technology. The detection voltage is fixed
internally with an accuracy of ±1.0% (VDET(S) 2.2 V). It operates with current consumption of 500 nA typ.
Apart from the power supply pin, the detection voltage input pin (SENSE pin) is also prepared, so the output is stable even
if the SENSE pin falls to 0 V.
The release signal can be delayed by setting a capacitor externally, and the release delay time accuracy at Ta = +25°C is
±15%.
Two output forms Nch open-drain output and CMOS output are available.
Features
Detection voltage:
1.0 V to 5.0 V (0.1 V step)
Detection voltage accuracy:
±1.0% (2.2 V ≤ −VDET(S) 5.0 V)
±22 mV (1.0 V ≤ −VDET(S) < 2.2 V)
Current consumption:
500 nA typ.
Operation voltage range:
0.95 V to 10.0 V
Hysteresis width:
5% ± 2%
Release delay time accuracy: ±15% (CD = 4.7 nF, Ta = +25°C)
Output form:
Nch open-drain output (Active "L")
CMOS output (Active "L")
Operation temperature range: Ta = 40°C to +85°C
Lead-free (Sn 100%), halogen-free
Applications
Power supply monitor for microcomputer and reset for CPU
Constant voltage power supply monitor for TV, Blu-ray recorder and home appliance
Power supply monitor for portable devices such as notebook PC, digital still camera and mobile phone
Packages
SOT-23-5
SNT-6A
Seiko Instruments Inc.
1


S-1004 Datasheet PDF
No Preview Available !

Click to Download PDF File for PC

BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR WITH SENSE PIN
S-1004 Series
Rev.2.1_00
Block Diagrams
1. S-1004 Series NA / NB type (Nch open-drain output)
SENSE
VDD
Function
Status
Output logic Active "L"
VSS
+
*1 *1
VREF
Delay
circuit
*1
OUT
*1
*1. Parasitic diode
CD
Figure 1
2. S-1004 Series CA / CB type (CMOS output)
SENSE
VDD
VSS
+
*1 *1
VREF
Delay
circuit
*1
Function
Status
Output logic Active "L"
*1
OUT
*1
*1. Parasitic diode
CD
Figure 2
2 Seiko Instruments Inc.


S-1004 Datasheet PDF
No Preview Available !

Click to Download PDF File for PC

BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR WITH SENSE PIN
Rev.2.1_00
S-1004 Series
Product Name Structure
Users can select the output form and detection voltage value for the S-1004 Series.
Refer to "1. Product name" regarding the contents of product name, "2. Function list of product types" regarding
the product types, "3. Packages" regarding the package drawings and "4. Product name list" regarding details of
product name.
1. Product name
S-1004 x x xx I - xxxx U
Environmental code
U: Lead-free (Sn 100%), halogen-free
Package abbreviation and IC packing specifications*1
M5T1: SOT-23-5, Tape
I6T1: SNT-6A, Tape
Operation temperature
I: Ta = 40°C to +85°C
Detection voltage value
10 to 50
(e.g., when the detection voltage is 1.0 V, it is expressed as 10.)
Pin configuration*2
A, B
Output form*3
N: Nch open-drain output (Active "L")*4
C: CMOS output (Active "L")*4
*1. Refer to the tape drawing.
*2. Refer to "Pin Configurations".
*3. Refer to "2. Function list of product types".
*4. If you request the product with output logic active "H", contact our sales office.
2. Function list of product types
Product Type
NA
NB
CA
CB
Output Form
Nch open-drain output
CMOS output
Table 1
Output Logic
Active "L"
Active "L"
Active "L"
Active "L"
Pin Configuration
A
B
A
B
Package
SOT-23-5, SNT-6A
SOT-23-5
SOT-23-5, SNT-6A
SOT-23-5
3. Packages
Package Name
SOT-23-5
SNT-6A
Table 2 Package Drawing Codes
Dimension
MP005-A-P-SD
PG006-A-P-SD
Tape
MP005-A-C-SD
PG006-A-C-SD
Reel
MP005-A-R-SD
PG006-A-R-SD
Land
PG006-A-L-SD
Seiko Instruments Inc.
3


S-1004 Datasheet PDF
No Preview Available !

Click to Download PDF File for PC

BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR WITH SENSE PIN
S-1004 Series
Rev.2.1_00
4. Product name list
4. 1 S-1004 Series NA type
Output form: Nch open-drain output (Active "L")
Detection Voltage
1.0 V ± 22 mV
1.1 V ± 22 mV
1.2 V ± 22 mV
1.3 V ± 22 mV
1.4 V ± 22 mV
1.5 V ± 22 mV
1.6 V ± 22 mV
1.7 V ± 22 mV
1.8 V ± 22 mV
1.9 V ± 22 mV
2.0 V ± 22 mV
2.1 V ± 22 mV
2.2 V ± 1.0%
2.3 V ± 1.0%
2.4 V ± 1.0%
2.5 V ± 1.0%
2.6 V ± 1.0%
2.7 V ± 1.0%
2.8 V ± 1.0%
2.9 V ± 1.0%
3.0 V ± 1.0%
3.1 V ± 1.0%
3.2 V ± 1.0%
3.3 V ± 1.0%
3.4 V ± 1.0%
3.5 V ± 1.0%
3.6 V ± 1.0%
3.7 V ± 1.0%
3.8 V ± 1.0%
3.9 V ± 1.0%
4.0 V ± 1.0%
4.1 V ± 1.0%
4.2 V ± 1.0%
4.3 V ± 1.0%
4.4 V ± 1.0%
4.5 V ± 1.0%
4.6 V ± 1.0%
4.7 V ± 1.0%
4.8 V ± 1.0%
4.9 V ± 1.0%
5.0 V ± 1.0%
Table 3
SOT-23-5
S-1004NA10I-M5T1U
S-1004NA11I-M5T1U
S-1004NA12I-M5T1U
S-1004NA13I-M5T1U
S-1004NA14I-M5T1U
S-1004NA15I-M5T1U
S-1004NA16I-M5T1U
S-1004NA17I-M5T1U
S-1004NA18I-M5T1U
S-1004NA19I-M5T1U
S-1004NA20I-M5T1U
S-1004NA21I-M5T1U
S-1004NA22I-M5T1U
S-1004NA23I-M5T1U
S-1004NA24I-M5T1U
S-1004NA25I-M5T1U
S-1004NA26I-M5T1U
S-1004NA27I-M5T1U
S-1004NA28I-M5T1U
S-1004NA29I-M5T1U
S-1004NA30I-M5T1U
S-1004NA31I-M5T1U
S-1004NA32I-M5T1U
S-1004NA33I-M5T1U
S-1004NA34I-M5T1U
S-1004NA35I-M5T1U
S-1004NA36I-M5T1U
S-1004NA37I-M5T1U
S-1004NA38I-M5T1U
S-1004NA39I-M5T1U
S-1004NA40I-M5T1U
S-1004NA41I-M5T1U
S-1004NA42I-M5T1U
S-1004NA43I-M5T1U
S-1004NA44I-M5T1U
S-1004NA45I-M5T1U
S-1004NA46I-M5T1U
S-1004NA47I-M5T1U
S-1004NA48I-M5T1U
S-1004NA49I-M5T1U
S-1004NA50I-M5T1U
SNT-6A
S-1004NA10I-I6T1U
S-1004NA11I-I6T1U
S-1004NA12I-I6T1U
S-1004NA13I-I6T1U
S-1004NA14I-I6T1U
S-1004NA15I-I6T1U
S-1004NA16I-I6T1U
S-1004NA17I-I6T1U
S-1004NA18I-I6T1U
S-1004NA19I-I6T1U
S-1004NA20I-I6T1U
S-1004NA21I-I6T1U
S-1004NA22I-I6T1U
S-1004NA23I-I6T1U
S-1004NA24I-I6T1U
S-1004NA25I-I6T1U
S-1004NA26I-I6T1U
S-1004NA27I-I6T1U
S-1004NA28I-I6T1U
S-1004NA29I-I6T1U
S-1004NA30I-I6T1U
S-1004NA31I-I6T1U
S-1004NA32I-I6T1U
S-1004NA33I-I6T1U
S-1004NA34I-I6T1U
S-1004NA35I-I6T1U
S-1004NA36I-I6T1U
S-1004NA37I-I6T1U
S-1004NA38I-I6T1U
S-1004NA39I-I6T1U
S-1004NA40I-I6T1U
S-1004NA41I-I6T1U
S-1004NA42I-I6T1U
S-1004NA43I-I6T1U
S-1004NA44I-I6T1U
S-1004NA45I-I6T1U
S-1004NA46I-I6T1U
S-1004NA47I-I6T1U
S-1004NA48I-I6T1U
S-1004NA49I-I6T1U
S-1004NA50I-I6T1U
4 Seiko Instruments Inc.


S-1004 Datasheet PDF
No Preview Available !

Click to Download PDF File for PC

BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR WITH SENSE PIN
Rev.2.1_00
S-1004 Series
4. 2 S-1004 Series NB type
Output form: Nch open-drain output (Active "L")
Table 4
Detection Voltage
1.0 V ± 22 mV
1.1 V ± 22 mV
1.2 V ± 22 mV
1.3 V ± 22 mV
1.4 V ± 22 mV
1.5 V ± 22 mV
1.6 V ± 22 mV
1.7 V ± 22 mV
1.8 V ± 22 mV
1.9 V ± 22 mV
2.0 V ± 22 mV
2.1 V ± 22 mV
2.2 V ± 1.0%
2.3 V ± 1.0%
2.4 V ± 1.0%
2.5 V ± 1.0%
2.6 V ± 1.0%
2.7 V ± 1.0%
2.8 V ± 1.0%
2.9 V ± 1.0%
3.0 V ± 1.0%
3.1 V ± 1.0%
3.2 V ± 1.0%
3.3 V ± 1.0%
3.4 V ± 1.0%
3.5 V ± 1.0%
3.6 V ± 1.0%
3.7 V ± 1.0%
3.8 V ± 1.0%
3.9 V ± 1.0%
4.0 V ± 1.0%
4.1 V ± 1.0%
4.2 V ± 1.0%
4.3 V ± 1.0%
4.4 V ± 1.0%
4.5 V ± 1.0%
4.6 V ± 1.0%
4.7 V ± 1.0%
4.8 V ± 1.0%
4.9 V ± 1.0%
5.0 V ± 1.0%
SOT-23-5
S-1004NB10I-M5T1U
S-1004NB11I-M5T1U
S-1004NB12I-M5T1U
S-1004NB13I-M5T1U
S-1004NB14I-M5T1U
S-1004NB15I-M5T1U
S-1004NB16I-M5T1U
S-1004NB17I-M5T1U
S-1004NB18I-M5T1U
S-1004NB19I-M5T1U
S-1004NB20I-M5T1U
S-1004NB21I-M5T1U
S-1004NB22I-M5T1U
S-1004NB23I-M5T1U
S-1004NB24I-M5T1U
S-1004NB25I-M5T1U
S-1004NB26I-M5T1U
S-1004NB27I-M5T1U
S-1004NB28I-M5T1U
S-1004NB29I-M5T1U
S-1004NB30I-M5T1U
S-1004NB31I-M5T1U
S-1004NB32I-M5T1U
S-1004NB33I-M5T1U
S-1004NB34I-M5T1U
S-1004NB35I-M5T1U
S-1004NB36I-M5T1U
S-1004NB37I-M5T1U
S-1004NB38I-M5T1U
S-1004NB39I-M5T1U
S-1004NB40I-M5T1U
S-1004NB41I-M5T1U
S-1004NB42I-M5T1U
S-1004NB43I-M5T1U
S-1004NB44I-M5T1U
S-1004NB45I-M5T1U
S-1004NB46I-M5T1U
S-1004NB47I-M5T1U
S-1004NB48I-M5T1U
S-1004NB49I-M5T1U
S-1004NB50I-M5T1U
Seiko Instruments Inc.
5


S-1004 Datasheet PDF
No Preview Available !

Click to Download PDF File for PC

BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR WITH SENSE PIN
S-1004 Series
Rev.2.1_00
4. 3 S-1004 Series CA type
Output form: CMOS output (Active "L")
Detection Voltage
1.0 V ± 22 mV
1.1 V ± 22 mV
1.2 V ± 22 mV
1.3 V ± 22 mV
1.4 V ± 22 mV
1.5 V ± 22 mV
1.6 V ± 22 mV
1.7 V ± 22 mV
1.8 V ± 22 mV
1.9 V ± 22 mV
2.0 V ± 22 mV
2.1 V ± 22 mV
2.2 V ± 1.0%
2.3 V ± 1.0%
2.4 V ± 1.0%
2.5 V ± 1.0%
2.6 V ± 1.0%
2.7 V ± 1.0%
2.8 V ± 1.0%
2.9 V ± 1.0%
3.0 V ± 1.0%
3.1 V ± 1.0%
3.2 V ± 1.0%
3.3 V ± 1.0%
3.4 V ± 1.0%
3.5 V ± 1.0%
3.6 V ± 1.0%
3.7 V ± 1.0%
3.8 V ± 1.0%
3.9 V ± 1.0%
4.0 V ± 1.0%
4.1 V ± 1.0%
4.2 V ± 1.0%
4.3 V ± 1.0%
4.4 V ± 1.0%
4.5 V ± 1.0%
4.6 V ± 1.0%
4.7 V ± 1.0%
4.8 V ± 1.0%
4.9 V ± 1.0%
5.0 V ± 1.0%
Table 5
SOT-23-5
S-1004CA10I-M5T1U
S-1004CA11I-M5T1U
S-1004CA12I-M5T1U
S-1004CA13I-M5T1U
S-1004CA14I-M5T1U
S-1004CA15I-M5T1U
S-1004CA16I-M5T1U
S-1004CA17I-M5T1U
S-1004CA18I-M5T1U
S-1004CA19I-M5T1U
S-1004CA20I-M5T1U
S-1004CA21I-M5T1U
S-1004CA22I-M5T1U
S-1004CA23I-M5T1U
S-1004CA24I-M5T1U
S-1004CA25I-M5T1U
S-1004CA26I-M5T1U
S-1004CA27I-M5T1U
S-1004CA28I-M5T1U
S-1004CA29I-M5T1U
S-1004CA30I-M5T1U
S-1004CA31I-M5T1U
S-1004CA32I-M5T1U
S-1004CA33I-M5T1U
S-1004CA34I-M5T1U
S-1004CA35I-M5T1U
S-1004CA36I-M5T1U
S-1004CA37I-M5T1U
S-1004CA38I-M5T1U
S-1004CA39I-M5T1U
S-1004CA40I-M5T1U
S-1004CA41I-M5T1U
S-1004CA42I-M5T1U
S-1004CA43I-M5T1U
S-1004CA44I-M5T1U
S-1004CA45I-M5T1U
S-1004CA46I-M5T1U
S-1004CA47I-M5T1U
S-1004CA48I-M5T1U
S-1004CA49I-M5T1U
S-1004CA50I-M5T1U
SNT-6A
S-1004CA10I-I6T1U
S-1004CA11I-I6T1U
S-1004CA12I-I6T1U
S-1004CA13I-I6T1U
S-1004CA14I-I6T1U
S-1004CA15I-I6T1U
S-1004CA16I-I6T1U
S-1004CA17I-I6T1U
S-1004CA18I-I6T1U
S-1004CA19I-I6T1U
S-1004CA20I-I6T1U
S-1004CA21I-I6T1U
S-1004CA22I-I6T1U
S-1004CA23I-I6T1U
S-1004CA24I-I6T1U
S-1004CA25I-I6T1U
S-1004CA26I-I6T1U
S-1004CA27I-I6T1U
S-1004CA28I-I6T1U
S-1004CA29I-I6T1U
S-1004CA30I-I6T1U
S-1004CA31I-I6T1U
S-1004CA32I-I6T1U
S-1004CA33I-I6T1U
S-1004CA34I-I6T1U
S-1004CA35I-I6T1U
S-1004CA36I-I6T1U
S-1004CA37I-I6T1U
S-1004CA38I-I6T1U
S-1004CA39I-I6T1U
S-1004CA40I-I6T1U
S-1004CA41I-I6T1U
S-1004CA42I-I6T1U
S-1004CA43I-I6T1U
S-1004CA44I-I6T1U
S-1004CA45I-I6T1U
S-1004CA46I-I6T1U
S-1004CA47I-I6T1U
S-1004CA48I-I6T1U
S-1004CA49I-I6T1U
S-1004CA50I-I6T1U
6 Seiko Instruments Inc.


S-1004 Datasheet PDF
No Preview Available !

Click to Download PDF File for PC

BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR WITH SENSE PIN
Rev.2.1_00
S-1004 Series
4. 4 S-1004 Series CB type
Output form: CMOS output (Active "L")
Table 6
Detection Voltage
1.0 V ± 22 mV
1.1 V ± 22 mV
1.2 V ± 22 mV
1.3 V ± 22 mV
1.4 V ± 22 mV
1.5 V ± 22 mV
1.6 V ± 22 mV
1.7 V ± 22 mV
1.8 V ± 22 mV
1.9 V ± 22 mV
2.0 V ± 22 mV
2.1 V ± 22 mV
2.2 V ± 1.0%
2.3 V ± 1.0%
2.4 V ± 1.0%
2.5 V ± 1.0%
2.6 V ± 1.0%
2.7 V ± 1.0%
2.8 V ± 1.0%
2.9 V ± 1.0%
3.0 V ± 1.0%
3.1 V ± 1.0%
3.2 V ± 1.0%
3.3 V ± 1.0%
3.4 V ± 1.0%
3.5 V ± 1.0%
3.6 V ± 1.0%
3.7 V ± 1.0%
3.8 V ± 1.0%
3.9 V ± 1.0%
4.0 V ± 1.0%
4.1 V ± 1.0%
4.2 V ± 1.0%
4.3 V ± 1.0%
4.4 V ± 1.0%
4.5 V ± 1.0%
4.6 V ± 1.0%
4.7 V ± 1.0%
4.8 V ± 1.0%
4.9 V ± 1.0%
5.0 V ± 1.0%
SOT-23-5
S-1004CB10I-M5T1U
S-1004CB11I-M5T1U
S-1004CB12I-M5T1U
S-1004CB13I-M5T1U
S-1004CB14I-M5T1U
S-1004CB15I-M5T1U
S-1004CB16I-M5T1U
S-1004CB17I-M5T1U
S-1004CB18I-M5T1U
S-1004CB19I-M5T1U
S-1004CB20I-M5T1U
S-1004CB21I-M5T1U
S-1004CB22I-M5T1U
S-1004CB23I-M5T1U
S-1004CB24I-M5T1U
S-1004CB25I-M5T1U
S-1004CB26I-M5T1U
S-1004CB27I-M5T1U
S-1004CB28I-M5T1U
S-1004CB29I-M5T1U
S-1004CB30I-M5T1U
S-1004CB31I-M5T1U
S-1004CB32I-M5T1U
S-1004CB33I-M5T1U
S-1004CB34I-M5T1U
S-1004CB35I-M5T1U
S-1004CB36I-M5T1U
S-1004CB37I-M5T1U
S-1004CB38I-M5T1U
S-1004CB39I-M5T1U
S-1004CB40I-M5T1U
S-1004CB41I-M5T1U
S-1004CB42I-M5T1U
S-1004CB43I-M5T1U
S-1004CB44I-M5T1U
S-1004CB45I-M5T1U
S-1004CB46I-M5T1U
S-1004CB47I-M5T1U
S-1004CB48I-M5T1U
S-1004CB49I-M5T1U
S-1004CB50I-M5T1U
Seiko Instruments Inc.
7


S-1004 Datasheet PDF
No Preview Available !

Click to Download PDF File for PC

BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR WITH SENSE PIN
S-1004 Series
Rev.2.1_00
Pin Configurations
1. S-1004 Series NA / CA type
1. 1 SOT-23-5
Top view
54
123
Figure 3
Pin No.
1
2
3
4
5
Table 7 Pin Configuration A
Symbol
OUT
VDD
VSS
CD
SENSE
Description
Voltage detection output pin
Power supply pin
GND pin
Connection pin for delay capacitor
Detection voltage input pin
1. 2 SNT-6A
Top view
16
25
34
Figure 4
Table 8 Pin Configuration A
Pin No.
Symbol
Description
1 OUT
Voltage detection output pin
2 VDD
Power supply pin
3 SENSE
Detection voltage input pin
4 CD
5 NC*1
Connection pin for delay capacitor
No connection
6 VSS
GND pin
*1. The NC pin is electrically open.
The NC pin can be connected to the VDD pin or the VSS pin.
2. S-1004 Series NB / CB type
2. 1 SOT-23-5
Top view
54
123
Figure 5
Pin No.
1
2
3
4
5
Table 9 Pin Configuration B
Symbol
OUT
VSS
VDD
SENSE
CD
Description
Voltage detection output pin
GND pin
Power supply pin
Detection voltage input pin
Connection pin for delay capacitor
8 Seiko Instruments Inc.


S-1004 Datasheet PDF
No Preview Available !

Click to Download PDF File for PC

BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR WITH SENSE PIN
Rev.2.1_00
S-1004 Series
Absolute Maximum Ratings
Table 10
Item Symbol
Power supply voltage
CD pin input voltage
SENSE pin input voltage
Output voltage
Nch open-drain output product
CMOS output product
VDD VSS
VCD
VSENSE
VOUT
Output current
Power dissipation
SOT-23-5
SNT-6A
IOUT
PD
Operation ambient temperature
Storage temperature
Topr
Tstg
*1. When mounted on board
[Mounted board]
(1) Board size: 114.3 mm × 76.2 mm × t1.6 mm
(2) Name:
JEDEC STANDARD51-7
(Ta = +25°C unless otherwise specified)
Absolute Maximum Rating
Unit
12.0
V
VSS 0.3 to VDD + 0.3
VSS 0.3 to 12.0
VSS 0.3 to 12.0
VSS 0.3 to VDD + 0.3
50
600*1
400*1
V
V
V
V
mA
mW
mW
40 to +85
°C
40 to +125
°C
Caution The absolute maximum ratings are rated values exceeding which the product could suffer
physical damage. These values must therefore not be exceeded under any conditions.
700
600
SOT-23-5
500
400 SNT-6A
300
200
100
0
0 50 100 150
Ambient Temperature (Ta) [°C]
Figure 6 Power Dissipation of Package (When Mounted on Board)
Seiko Instruments Inc.
9


S-1004 Datasheet PDF
No Preview Available !

Click to Download PDF File for PC

BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR WITH SENSE PIN
S-1004 Series
Rev.2.1_00
Electrical Characteristics
1. Nch open-drain output product
Table 11
(Ta = +25°C unless otherwise specified)
Item Symbol
Condition
Min.
Typ.
Max.
Unit
Test
Circuit
Detection voltage*1 VDET
0.95 V VDD 10.0 V
1.0 V ≤ −VDET(S) < 2.2 V
2.2 V ≤ −VDET(S) 5.0 V
VDET(S)
0.022
VDET(S)
× 0.99
VDET(S)
VDET(S)
VDET(S)
+ 0.022
VDET(S)
× 1.01
V
V
Hysteresis width VHYS
VDET VDET VDET
× 0.03 × 0.05 × 0.07
V
Current
consumption*2
ISS
VDD = 10.0 V, VSENSE = VDET(S) + 1.0 V
0.50 0.90 μA
Operation voltage VDD
0.95 10.0 V
Output transistor
VDD = 0.95 V
0.59 1.00 mA
Output current
IOUT
Nch
VDS*3 = 0.5 V
VSENSE = 0.0 V
VDD = 1.2 V
VDD = 2.4 V
VDD = 4.8 V
0.73 1.33 mA
1.47 2.39 mA
1.86 2.50 mA
Output transistor
Leakage current ILEAK
Nch
VDD = 10.0 V, VDS*3 = 10.0 V, VSENSE = 10.0 V
0.08 μA
Detection voltage
temperature
coefficient*4
Δ−VDET
ΔTa • −VDET
Ta
=
40°C
to
+85°C
− ±100 ±350 ppm/°C
1
1
1
2
1
3
3
3
3
3
1
Detection
delay time*5
Release
delay time*6
tDET
tRESET
VDD = 5.0 V
VDD = VDET(S) + 1.0 V, CD = 4.7 nF
40
10.79 12.69 14.59
μs
ms
4
4
SENSE pin
resistance
RSENSE
1.0 V ≤ −VDET(S) < 1.2 V
1.2 V ≤ −VDET(S) 5.0 V
5.0 19.0 42.0 MΩ 2
6.0 30.0 98.0 MΩ 2
*1. VDET: Actual detection voltage value, VDET(S): Set detection voltage value (the center value of the detection voltage
range in Table 3 or Table 4)
*2. The current flowing through the SENSE pin resistance is not included.
*3. VDS: Drain-to-source voltage of the output transistor
*4. The temperature change of the detection voltage [mV/°C] is calculated by using the following equation.
Δ−VDET
ΔTa
[mV/°C]*1 = VDET(S) (typ.)[V]*2 ×
Δ−VDET
ΔTa • −VDET
[ppm/°C]*3 ÷ 1000
*1. Temperature change of the detection voltage
*2. Set detection voltage
*3. Detection voltage temperature coefficient
*5. The time period from when the pulse voltage of 6.0 V → −VDET(S) 2.0 V or 0 V is applied to the SENSE pin to when
VOUT reaches VDD / 2, after the output pin is pulled up to 5.0 V by the resistance of 470 kΩ.
*6. The time period from when the pulse voltage of 0.95 V 10.0 V is applied to the SENSE pin to when VOUT reaches
VDD × 90%, after the output pin is pulled up to VDD by the resistance of 100 kΩ.
10 Seiko Instruments Inc.


S-1004 Datasheet PDF
No Preview Available !

Click to Download PDF File for PC

BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR WITH SENSE PIN
Rev.2.1_00
S-1004 Series
2. CMOS output product
Table 12
(Ta = +25°C unless otherwise specified)
Item Symbol
Condition
Min.
Typ.
Max.
Unit
Test
Circuit
Detection voltage*1 VDET
0.95 V VDD 10.0 V
1.0 V ≤ −VDET(S) < 2.2 V
2.2 V ≤ −VDET(S) 5.0 V
VDET(S)
0.022
VDET(S)
× 0.99
VDET(S)
VDET(S)
VDET(S)
+ 0.022
VDET(S)
× 1.01
V
V
Hysteresis width VHYS
VDET VDET VDET
× 0.03 × 0.05 × 0.07
V
Current
consumption*2
ISS
VDD = 10.0 V, VSENSE = VDET(S) + 1.0 V
0.50 0.90 μA
Operation voltage VDD
0.95 10.0 V
Output transistor
VDD = 0.95 V
0.59 1.00 mA
Output current
IOUT
Nch
VDS*3 = 0.5 V
VSENSE = 0.0 V
Output transistor
Pch
VDS*3 = 0.5 V
VSENSE = 10.0 V
VDD = 1.2 V
VDD = 2.4 V
VDD = 4.8 V
VDD = 4.8 V
VDD = 6.0 V
0.73 1.33 mA
1.47 2.39 mA
1.86 2.50 mA
1.62 2.60 mA
1.78 2.86 mA
Detection voltage
temperature
coefficient*4
Δ−VDET
ΔTa • −VDET
Ta
=
40°C
to
+85°C
− ±100 ±350 ppm/°C
Detection
delay time*5
tDET
VDD = 5.0 V
40 − μs
1
1
1
2
1
3
3
3
3
5
5
1
4
Release
delay time*6
tRESET
VDD = VDET(S) + 1.0 V, CD = 4.7 nF
10.79 12.69 14.59 ms
4
SENSE pin
resistance
RSENSE
1.0 V ≤ −VDET(S) < 1.2 V
1.2 V ≤ −VDET(S) 5.0 V
5.0 19.0 42.0 MΩ 2
6.0 30.0 98.0 MΩ 2
*1. VDET: Actual detection voltage value, VDET(S): Set detection voltage value (the center value of the detection voltage
range in Table 5 or Table 6)
*2. The current flowing through the SENSE pin resistance is not included.
*3. VDS: Drain-to-source voltage of the output transistor
*4. The temperature change of the detection voltage [mV/°C] is calculated by using the following equation.
Δ−VDET
ΔTa
[mV/°C]*1 = VDET(S) (typ.)[V]*2 ×
Δ−VDET
ΔTa • −VDET
[ppm/°C]*3 ÷ 1000
*1. Temperature change of the detection voltage
*2. Set detection voltage
*3. Detection voltage temperature coefficient
*5. The time period from when the pulse voltage of 6.0 V → −VDET(S) 2.0 V or 0 V is applied to the SENSE pin to when
VOUT reaches VDD / 2.
*6. The time period from when the pulse voltage of 0.95 V 10.0 V is applied to the SENSE pin to when VOUT reaches
VDD × 90%.
Seiko Instruments Inc.
11


S-1004 Datasheet PDF
No Preview Available !

Click to Download PDF File for PC

BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR WITH SENSE PIN
S-1004 Series
Rev.2.1_00
Test Circuits
VDD
VDD
R
100 kΩ
VDD
VDD
SENSE OUT
SENSE OUT
+
V
VSS CD
+
V
+
V
VSS CD
+
V
Figure 7 Test Circuit 1
(Nch open-drain output product)
+A
VDD
+
A
VDD
SENSE OUT
VSS CD
Figure 8 Test Circuit 1
(CMOS output product)
VDD
VDD +
V SENSE OUT
VSS CD
+
A
+
V
VDS
Figure 9 Test Circuit 2
Figure 10 Test Circuit 3
VDD
P.G.
VDD
SENSE OUT
VSS CD
R
470 kΩ or 100 kΩ
Oscilloscope
VDD
P.G.
VDD
SENSE OUT
VSS CD
Oscilloscope
Figure 11 Test Circuit 4
(Nch open-drain output product)
VDD
VDD
+
V SENSE OUT
VSS CD
+
V
+
A
VDS
Figure 12 Test Circuit 4
(CMOS output product)
Figure 13 Test Circuit 5
12 Seiko Instruments Inc.


S-1004 Datasheet PDF
No Preview Available !

Click to Download PDF File for PC

BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR WITH SENSE PIN
Rev.2.1_00
S-1004 Series
Standard Circuits
1. Nch open-drain output product
VDD
SENSE
VSS
OUT
CD
CD*1
R
100 kΩ
*1. The delay capacitor (CD) should be connected directly to the CD pin and the VSS pin.
Figure 14
2. CMOS output product
VDD
SENSE
VSS
OUT
CD
CD*1
*1. The delay capacitor (CD) should be connected directly to the CD pin and the VSS pin.
Figure 15
Caution The above connection diagram and constant will not guarantee successful operation.
Perform thorough evaluation using the actual application to set the constant.
Seiko Instruments Inc.
13


S-1004 Datasheet PDF
No Preview Available !

Click to Download PDF File for PC

BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR WITH SENSE PIN
S-1004 Series
Rev.2.1_00
Explanation of Terms
1. Detection voltage (VDET)
The detection voltage is a voltage at which the output in Figure 18 or Figure 19 turns to "L". The detection voltage
varies slightly among products of the same specification. The variation of detection voltage between the specified
minimum (VDET min.) and the maximum (VDET max.) is called the detection voltage range (Refer to Figure 16).
Example: In the S-1004Cx18, the detection voltage is either one in the range of 1.778 V ≤ −VDET 1.822 V.
This means that some S-1004Cx18 have VDET = 1.778 V and some have VDET = 1.822 V.
2. Release voltage (+VDET)
The release voltage is a voltage at which the output in Figure 18 or Figure 19 turns to "H". The release voltage
varies slightly among products of the same specification. The variation of release voltage between the specified
minimum (+VDET min.) and the maximum (+VDET max.) is called the release voltage range (Refer to Figure 17). The
range is calculated from the actual detection voltage (VDET) of a product and is in the range of VDET × 1.03
+VDET ≤ −VDET × 1.07.
Example: For the S-1004Cx18, the release voltage is either one in the range of 1.832 V ≤ +VDET 1.949 V.
This means that some S-1004Cx18 have +VDET = 1.832 V and some have +VDET = 1.949 V.
VSENSE
VDET max.
VDET min.
Detection voltage
Detection voltage
range
Release voltage
+VDET max.
+VDET min.
VSENSE
Release voltage
range
VOUT
tDET
Figure 16 Detection Voltage
VOUT
tRESET
Figure 17 Release Voltage
VDD
VDD
R
100 kΩ
VDD
VDD
SENSE OUT
SENSE OUT
+
V
VSS CD
+
V
+
V
VSS CD
+
V
Figure 18 Test Circuit of Detection Voltage
and Release Voltage
(Nch open-drain output product)
Figure 19 Test Circuit of Detection Voltage
and Release Voltage
(CMOS output product)
14 Seiko Instruments Inc.


S-1004 Datasheet PDF
No Preview Available !

Click to Download PDF File for PC

BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR WITH SENSE PIN
Rev.2.1_00
S-1004 Series
3. Hysteresis width (VHYS)
The hysteresis width is the voltage difference between the detection voltage and the release voltage (the voltage at
point B the voltage at point A = VHYS in "Figure 23 Timing Chart of S-1004 Series NA / NB Type" and "Figure
25 Timing Chart of S-1004 Series CA / CB Type"). Setting the hysteresis width between the detection voltage
and the release voltage, prevents malfunction caused by noise on the input voltage.
4. Release delay time (tRESET)
The release delay time is the time period from when the input voltage to the SENSE pin exceeds the release
voltage (+VDET) to when the output from the OUT pin inverts. The release delay time changes according to the
delay capacitor (CD).
VSENSE
+VDET
OUT
tRESET
Figure 20 Release Delay Time
5. Feed-through current
The feed-through current is a current that flows instantaneously to the VDD pin at the time of detection and release
of a voltage detector. The feed-through current is large in CMOS output product, small in Nch open-drain output
product.
6. Oscillation
In applications where an input resistor is connected (Figure 21), taking a CMOS output (active "L") product for
example, the feed-through current which is generated when the output goes from "L" to "H" (at the time of release)
causes a voltage drop equal to [feed-through current] × [input resistance]. Since the VDD pin and the SENSE pin
are shorted as in Figure 21, the SENSE pin voltage drops at the time of release. Then the SENSE pin voltage
drops below the detection voltage and the output goes from "H" to "L". In this status, the feed-through current stops
and its resultant voltage drop disappears, and the output goes from "L" to "H". The feed-through current is then
generated again, a voltage drop appears, and repeating the process finally induces oscillation.
VDD
RA
VIN
RB
VDD
SENSE OUT
VSS CD
(CMOS output product)
GND
Figure 21 Example for Bad Implementation Due to Detection Voltage Change
Seiko Instruments Inc.
15


S-1004 Datasheet PDF
No Preview Available !

Click to Download PDF File for PC

BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR WITH SENSE PIN
S-1004 Series
Rev.2.1_00
Operation
1. Basic operation
1. 1 S-1004 Series NA / NB type
(1) When the power supply voltage (VDD) is the minimum operation voltage or higher, and the SENSE pin voltage
(VSENSE) is the release voltage (+VDET) or higher, the Nch transistor is turned off to output VDD ("H") when the
output is pulled up. Since the Nch transistor (N1) is turned off, the input voltage to the comparator is
(RB +
RA
RC ) VSENSE
+ RB + RC
.
(2) Even if VSENSE decreases to +VDET or lower, VDD is output when VSENSE is higher than the detection voltage
(VDET).
When VSENSE decreases to VDET or lower (point A in Figure 23), the Nch transistor is turned on. And then VSS
("L") is output from the OUT pin after the elapse of the detection delay time (tDET).
At this time, N1 is turned on, and the input voltage to the comparator is
RB
RA
VSENSE
+ RB
.
(3) Even if VSENSE further decreases to the IC's minimum operation voltage or lower, the output from the OUT pin is
stable when VDD is minimum operation voltage or higher.
(4) Even if VSENSE exceeds VDET, VSS is output when VSENSE is lower than +VDET.
(5) When VSENSE increases to +VDET or higher (point B in Figure 23), the Nch transistor is turned off. And then VDD
is output from the OUT pin after the elapse of the release delay time (tRESET) when the output is pulled up.
VDD
VDD
VSENSE
VSS
SENSE
RA
*1 *1
VREF
RB
RC
+
N1
Delay
circuit
Nch
*1
OUT
R
100 kΩ
*1
+
V
CD
CD
*1. Parasitic diode
Figure 22 Operation of S-1004 Series NA / NB Type
(1) (2) (3) (4) (5)
Hysteresis width
(VHYS)
VSENSE
A
B Release voltage (+VDET)
Detection voltage (VDET)
Minimum operation voltage
VSS
Output from OUT pin
VDD
VSS
tDET
tRESET
Figure 23 Timing Chart of S-1004 Series NA / NB Type
16 Seiko Instruments Inc.


S-1004 Datasheet PDF
No Preview Available !

Click to Download PDF File for PC

BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR WITH SENSE PIN
Rev.2.1_00
S-1004 Series
1. 2 S-1004 Series CA / CB type
(1) When the power supply voltage (VDD) is the minimum operation voltage or higher, and the SENSE pin voltage
(VSENSE) is the release voltage (+VDET) or higher, the Nch transistor is turned off and the Pch transistor is turned
on to output VDD ("H"). Since the Nch transistor (N1) is turned off, the input voltage to the comparator is
(RB +
RA
RC ) VSENSE
+ RB + RC
.
(2) Even if VSENSE decreases to +VDET or lower, VDD is output when VSENSE is higher than the detection voltage
(VDET).
When VSENSE decreases to VDET or lower (point A in Figure 25), the Nch transistor is turned on and the Pch
transistor is turned off. And then VSS ("L") is output from the OUT pin after the elapse of the detection delay time
(tDET).
At this time, N1 is turned on, and the input voltage to the comparator is
RB
RA
VSENSE
+ RB
.
(3) Even if VSENSE further decreases to the IC's minimum operation voltage or lower, the output from the OUT pin is
stable when VDD is minimum operation voltage or higher.
(4) Even if VSENSE exceeds VDET, VSS is output when VSENSE is lower than +VDET.
(5) When VSENSE increases to +VDET or higher (point B in Figure 25), the Nch transistor is turned off and the Pch
transistor is turned on. And then VDD is output from the OUT pin after the elapse of the release delay time
(tRESET).
VDD
SENSE
VDD
VSENSE
VSS
RA
*1 *1
VREF
RB
RC
+
N1
Delay
circuit
Pch
Nch
*1
*1
OUT
*1
+
V
CD
CD
*1. Parasitic diode
Figure 24 Operation of S-1004 Series CA / CB Type
(1) (2) (3) (4) (5)
Hysteresis width
(VHYS)
VSENSE
A
B Release voltage (+VDET)
Detection voltage (VDET)
Minimum operation voltage
VSS
Output from OUT pin
VDD
VSS
tDET
tRESET
Figure 25 Timing Chart of S-1004 Series CA / CB Type
Seiko Instruments Inc.
17


S-1004 Datasheet PDF
No Preview Available !

Click to Download PDF File for PC

BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR WITH SENSE PIN
S-1004 Series
Rev.2.1_00
2. SENSE pin
2. 1 Error when detection voltage is set externally
By connecting a node that was resistance-divided by the resistor (RA) and the resistor (RB) to the SENSE pin as
seen in Figure 26, the detection voltage can be set externally.
For conventional products without the SENSE pin, RA cannot be too large since the resistance-divided node must
be connected to the VDD pin. This is because a feed-through current will flow through the VDD pin when it goes
from detection to release, and if RA is large, problems such as oscillation or larger error in the hysteresis width may
occur.
In the S-1004 Series, RA and RB are easily made larger since the resistance-divided node can be connected to the
SENSE pin through which no feed-through current flows. However, be careful of error in the current flowing through
the internal resistance (RSENSE) that will occur.
Although RSENSE in the S-1004 Series is large (5 MΩ min.) to make the error small, RA and RB should be selected
such that the error is within the allowable limits.
2. 2 Selection of RA and RB
In Figure 26, the relation between the external setting detection voltage (VDX) and the actual detection voltage
(VDET) is ideally calculated by the equation below.
( )VDX = VDET ×
1+
RA
RB
··· (1)
However, in reality there is an error in the current flowing through RSENSE.
When considering this error, the relation between VDX and VDET is calculated as follows.
(VDX = VDET × 1 +
= VDET ×
1
+
(= VDET × 1 +
)RA
RB || RSENSE
RA
RB × RSENSE
RB + RSENSE
)RA
RB
+
RA
RSENSE
× −VDET
··· (2)
By using equations (1) and (2), the error is calculated as VDET ×
RA
RSENSE
.
The error rate is calculated as follows by dividing the error by the right-hand side of equation (1).
RA × RB
RSENSE × (RA + RB)
× 100 [%] =
RA || RB
RSENSE
× 100 [%]
··· (3)
As seen in equation (3), the smaller the resistance values of RA and RB compared to RSENSE, the smaller the error
rate becomes.
Also, the relation between the external setting hysteresis width (VHX) and the hysteresis width (VHYS) is calculated
by equation below. Error due to RSENSE also occurs to the relation in a similar way to the detection voltage.
( )VHX = VHYS ×
1+
RA
RB
··· (4)
VDX
RA
VDET
RB
VDD
SENSE
RSENSE
VSS
OUT
CD
Figure 26 Detection Voltage External Setting Circuit
Caution
18
If RA and RB are large, the SENSE pin input impedance becomes higher and may cause a
malfunction due to noise. In this case, connect a capacitor between the SENSE pin and the VSS
pin.
Seiko Instruments Inc.


S-1004 Datasheet PDF
No Preview Available !

Click to Download PDF File for PC

BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR WITH SENSE PIN
Rev.2.1_00
S-1004 Series
2. 3 Power on sequence
Apply power in the order, the VDD pin then the SENSE pin.
As seen in Figure 27, when VSENSE ≥ +VDET, the OUT pin output (VOUT) rises and the S-1004 Series becomes the
release status (normal operation).
VDD
VSENSE
+VDET
VOUT
tRESET
Figure 27
Caution If power is applied in the order the SENSE pin then the VDD pin, an erroneous release may occur
even if VSENSE < +VDET.
2. 4 Precautions when shorting between the VDD pin and the SENSE pin
2. 4. 1 Input resistor
Do not connect the input resistor (RA) when shorting between the VDD pin and the SENSE pin.
A feed-through current flows through the VDD pin at the time of release. When connecting the circuit shown as
Figure 28, the feed-through current of the VDD pin flowing through RA will cause a drop in VSENSE at the time of
release.
At that time, oscillation may occur if VSENSE ≤ −VDET.
RA
VDD
SENSE
OUT
VDD CD
VSS
Figure 28
2. 4. 2 Parasitic resistance and parasitic capacitance
Due to the difference in parasitic resistance and parasitic capacitance of the VDD pin and the SENSE pin,
power may be applied to the SENSE pin first.
Note that an erroneous release may occur if this happens (refer to "2. 3 Power on sequence").
Caution
In CMOS output product, make sure that the VDD pin input impedance does not become too
high, regardless of the above. Since a feed-through current is large, a malfunction may occur if
the VDD pin voltage changes greatly at the time of release.
Seiko Instruments Inc.
19


S-1004 Datasheet PDF
No Preview Available !

Click to Download PDF File for PC

BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR WITH SENSE PIN
S-1004 Series
Rev.2.1_00
2. 5 Malfunction when VDD falls
As seen in Figure 29, note that if the VDD pin voltage (VDD) drops steeply below 1.2 V when VDET < VSENSE <
+VDET, erroneous detection may occur.
When VDD_Low 1.2 V, erroneous detection does not occur.
When VDD_Low < 1.2 V, the more the VDD falling amplitude increases or the shorter the falling time becomes, the
easier the erroneous detection.
Perform thorough evaluation in actual application.
VDD
VDD_High
VDD_Low (Voltage drops below 1.2 V.)
VSENSE
+VDET
VDET
VOUT
VOUT falling influenced by VDD falling
(erroneous detection)
Figure 29
The S-1004Cx50 example in Figure 30 shows an example of erroneous detection boundary conditions.
Remark
12
10
8 Danger of erroneous
6 detection
4
2
0
0.1
1 10 100 1000
tF [s]
Figure 30
Test conditions
Product name: S-1004Cx50
VSENSE:
VDET(S) + 0.1 V
VDD_High:
VDD pin voltage before falling
VDD_Low:
VDD pin voltage after falling (0.95 V)
ΔVDD:
VDD_High VDD_Low
tF: Falling time of VDD from VDD_High − ΔVDD × 10% to VDD_Low + ΔVDD × 10%
VDD_High
VDD_High  VDD 10%
VDD
VDD_Low  VDD 10%
VDD_Low
tF
Figure 31
20 Seiko Instruments Inc.


S-1004 Datasheet PDF
No Preview Available !

Click to Download PDF File for PC

BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR WITH SENSE PIN
Rev.2.1_00
S-1004 Series
3. Delay circuit
The delay circuit has the function that adjusts the release delay time (tRESET) from when the SENSE pin voltage
(VSENSE) reaches release voltage (+VDET) to when the output from OUT pin inverts.
tRESET is determined by the delay coefficient, the delay capacitor (CD), and the release delay time when the CD pin
is open (tRESET0), and calculated by the equation below.
tRESET [ms] = Delay coefficient × CD [nF] + tRESET0 [ms]
Operation
Temperature
Ta = +85°C
Ta = +25°C
Ta = 40°C
Table 13
Delay Coefficient
Min. Typ.
1.78 2.29
2.30 2.66
2.68 3.09
Max.
3.13
3.07
3.57
Operation
Temperature
Ta = +85°C
Ta = +25°C
Ta = 40°C
Table 14
Release Delay Time when CD Pin is Open (tRESET0)
Min. Typ. Max.
0.020 ms
0.049 ms
0.130 ms
0.021 ms
0.059 ms
0.164 ms
0.024 ms
0.074 ms
0.202 ms
Caution 1.
2.
3.
Mounted board layout should be made in such a way that no current flows into or flows from
the CD pin since the impedance of the CD pin is high, otherwise correct delay time cannot be
provided.
There is no limit for the capacitance of CD as long as the leakage current of the capacitor can
be ignored against the built-in constant current value (30 nA to 200 nA).
The detection delay time (tDET) cannot be adjusted by CD.
Seiko Instruments Inc.
21


S-1004 Datasheet PDF
No Preview Available !

Click to Download PDF File for PC

BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR WITH SENSE PIN
S-1004 Series
Rev.2.1_00
4. Other characteristics
4. 1 Temperature characteristics of detection voltage
The shaded area in Figure 32 shows the temperature characteristics of detection voltage in the operation
temperature range.
VDET [V]
+0.945 mV/°C
VDET25*1
0.945 mV/°C
40 +25 +85 Ta [°C]
*1. VDET25 is a detection voltage value at Ta = +25°C.
Figure 32 Temperature Characteristics of Detection Voltage (Example for VDET = 2.7 V)
4. 2 Temperature characteristics of release voltage
The temperature change
Δ+VDET
ΔTa
of the release voltage is calculated by using the temperature change
Δ−VDET
ΔTa
of the detection voltage as follows:
Δ+VDET
ΔTa
=
+VDET
VDET
×
Δ−VDET
ΔTa
The temperature change of the release voltage and the detection voltage has the same sign consequently.
4. 3 Temperature characteristics of hysteresis voltage
The temperature change of the hysteresis voltage is expressed as
Δ+VDET
ΔTa
Δ−VDET
ΔTa
and is calculated as
follows:
Δ+VDET
ΔTa
Δ−VDET
ΔTa
=
VHYS
VDET
×
Δ−VDET
ΔTa
22 Seiko Instruments Inc.


S-1004 Datasheet PDF
No Preview Available !

Click to Download PDF File for PC

BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR WITH SENSE PIN
Rev.2.1_00
S-1004 Series
Precautions
Do not apply an electrostatic discharge to this IC that exceeds the performance ratings of the built-in electrostatic
protection circuit.
In CMOS output product of the S-1004 Series, the feed-through current flows at the time of detection and release. If
the VDD pin input impedance is high, malfunction may occur due to the voltage drop by the feed-through current
when releasing.
In CMOS output product, oscillation may occur if a pull-down resistor is connected and falling speed of the SENSE
pin voltage (VSENSE) is slow near the detection voltage when the VDD pin and the SENSE pin are shorted.
When designing for mass production using an application circuit described herein, the product deviation and
temperature characteristics of the external parts should be taken into consideration. SII shall not bear any
responsibility for patent infringements related to products using the circuits described herein.
SII claims no responsibility for any disputes arising out of or in connection with any infringement by products
including this IC of patents owned by a third party.
Seiko Instruments Inc.
23


S-1004 Datasheet PDF
No Preview Available !

Click to Download PDF File for PC

BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR WITH SENSE PIN
S-1004 Series
Rev.2.1_00
Characteristics (Typical Data)
1. Detection voltage (VDET), Release voltage (+VDET) vs. Temperature (Ta)
S-1004Cx10
1.2
VDD = 5.0 V
S-1004Cx24
2.6
1.1 VDET
VDET
2.5
1.0
VDET
0.9
2.4
VDET
2.3
VDD = 5.0 V
0.8
40 25
0 25
Ta [C]
50
75 85
2.2
40 25
0 25
Ta [C]
50
75 85
S-1004Cx50
5.4
5.2
VDET
VDD = 5.0 V
5.0
VDET
4.8
4.6
40 25
0 25
Ta [C]
50
75 85
2. Hysteresis width (VHYS) vs. Temperature (Ta)
S-1004Cx10
7.0
VDD = 5.0 V
S-1004Cx24
7.0
VDD = 5.0 V
6.0 6.0
5.0 5.0
4.0 4.0
3.0
40 25
0 25
Ta [C]
50
75 85
3.0
40 25
0 25
Ta [C]
50
75 85
S-1004Cx50
7.0
VDD = 5.0 V
6.0
5.0
4.0
3.0
40 25
0 25
Ta [C]
50
75 85
24 Seiko Instruments Inc.


S-1004 Datasheet PDF
No Preview Available !

Click to Download PDF File for PC

BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR WITH SENSE PIN
Rev.2.1_00
S-1004 Series
3. Detection voltage (VDET) vs. Power supply voltage (VDD)
S-1004Cx10
1.030
S-1004Cx24
2.430
1.020
1.010
1.000
Ta = 25C
2.420
2.410
2.400
Ta = 25C
Ta = 40C
Ta = 85C
0.990
2.390
0.980
0.970
Ta = 40C
0.0 2.0 4.0
Ta = 85C
6.0 8.0 10.0
VDD [V]
2.380
2.370
0.0 2.0 4.0 6.0 8.0 10.0
VDD [V]
S-1004Cx50
5.050
5.025
5.000
Ta = 25C
Ta = 40C
Ta = 85C
4.975
4.950
0.0 2.0 4.0 6.0 8.0 10.0
VDD [V]
4. Hysteresis width (VHYS) vs. Power supply voltage (VDD)
S-1004Cx10
7.0
S-1004Cx24
7.0
6.0 Ta = 25C
Ta = 40C
6.0
Ta = 25C
5.0 5.0
4.0
3.0
0.0
Ta = 85C
2.0 4.0 6.0
VDD [V]
8.0 10.0
4.0
3.0
0.0
Ta = 40C Ta = 85C
2.0 4.0 6.0 8.0 10.0
VDD [V]
S-1004Cx50
7.0
6.0 Ta = 85C
5.0
4.0
Ta = 25C
Ta = 40C
3.0
0.0 2.0 4.0 6.0 8.0 10.0
VDD [V]
Seiko Instruments Inc.
25


S-1004 Datasheet PDF
No Preview Available !

Click to Download PDF File for PC

BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR WITH SENSE PIN
S-1004 Series
Rev.2.1_00
5. Current consumption (ISS) vs. Power supply voltage (VDD)
S-1004Cx10
Ta = +25°C,
VSENSE = VDET(S) 0.1 V (during detection)
1.00
S-1004Cx10
Ta = +25°C,
VSENSE = VDET(S) + 1.0 V (during release)
1.00
0.80 0.80
0.60 0.60
0.40 0.40
0.20 0.20
0.00
0.0 2.0 4.0 6.0 8.0 10.0
VDD [V]
0.00
0.0 2.0 4.0 6.0 8.0 10.0
VDD [V]
S-1004Cx24
Ta = +25°C,
VSENSE = VDET(S) 0.1 V (during detection)
1.00
0.80
0.60
0.40
0.20
0.00
0.0 2.0 4.0 6.0 8.0 10.0
VDD [V]
S-1004Cx24
Ta = +25°C,
VSENSE = VDET(S) + 1.0 V (during release)
1.00
0.80
0.60
0.40
0.20
0.00
0.0 2.0 4.0 6.0 8.0 10.0
VDD [V]
S-1004Cx50
Ta = +25°C,
VSENSE = VDET(S) 0.1 V (during detection)
1.00
0.80
0.60
0.40
0.20
0.00
0.0 2.0 4.0 6.0 8.0 10.0
VDD [V]
S-1004Cx50
Ta = +25°C,
VSENSE = VDET(S) + 1.0 V (during release)
1.00
0.80
0.60
0.40
0.20
0.00
0.0 2.0 4.0 6.0 8.0 10.0
VDD [V]
26 Seiko Instruments Inc.


S-1004 Datasheet PDF
No Preview Available !

Click to Download PDF File for PC

BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR WITH SENSE PIN
Rev.2.1_00
S-1004 Series
6. Current consumption (ISS) vs. SENSE pin input voltage (VSENSE)
S-1004Cx10
Ta = +25°C,
VDD = VDET(S) + 1.0 V, VSENSE = 0.0 V 10.0 V
1.00
S-1004Cx24
Ta = +25°C,
VDD = VDET(S) + 1.0 V, VSENSE = 0.0 V 10.0 V
1.00
0.80 0.80
0.60 0.60
0.40 0.40
0.20 0.20
0.00
0.0 2.0 4.0 6.0 8.0 10.0
VSENSE [V]
0.00
0.0 2.0 4.0 6.0 8.0 10.0
VSENSE [V]
S-1004Cx50
Ta = +25°C,
VDD = VDET(S) + 1.0 V, VSENSE = 0.0 V 10.0 V
1.00
0.80
0.60
0.40
0.20
0.00
0.0 2.0 4.0 6.0 8.0 10.0
VSENSE [V]
7. Current consumption (ISS) vs. Temperature (Ta)
S-1004Cx10
VDD = VDET(S) + 1.0 V,
VSENSE = VDET(S) + 1.0 V (during release)
0.30
S-1004Cx24
VDD = VDET(S) + 1.0 V,
VSENSE = VDET(S) + 1.0 V (during release)
0.30
0.25 0.25
0.20 0.20
0.15 0.15
0.10 0.10
0.05 0.05
0.00
40 25
0 25
Ta [C]
50
75 85
0.00
40 25
0 25
Ta [C]
50
75 85
S-1004Cx50
VDD = VDET(S) + 1.0 V,
VSENSE = VDET(S) + 1.0 V (during release)
0.30
0.25
0.20
0.15
0.10
0.05
0.00
40 25
0 25
Ta [C]
50
75 85
Seiko Instruments Inc.
27


S-1004 Datasheet PDF
No Preview Available !

Click to Download PDF File for PC

BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR WITH SENSE PIN
S-1004 Series
Rev.2.1_00
8. Nch transistor output current (IOUT) vs. VDS
S-1004Nx12
20.0
15.0
Ta = +25°C,
VSENSE = 0.0 V (during detection)
VDD = 4.8 V VDD = 6.0 V
10.0
5.0
0.0
0.0
VDD = 3.6 V
VDD = 2.4 V
VDD = 1.2 V
VDD = 0.95 V
1.0 2.0 3.0 4.0 5.0 6.0
VDS [V]
9. Pch transistor output current (IOUT) vs. VDS
S-1004Cx12
Ta = +25°C,
VSENSE = VDET(S) + 1.0 V (during release)
40.0
VDD = 8.4 V
30.0
VDD = 0.95 V
VDD = 1.2 V
VDD = 7.2 V
20.0
VDD = 6.0 V
10.0
0.0
0.0
VDD = 4.8 V
VDD = 3.6 V
VDD = 2.4 V
2.0 4.0 6.0 8.0
10.0
VDS [V]
10. Nch transistor output current (IOUT) vs. Power supply voltage (VDD)
S-1004Nx12
4.0
VDS = 0.5 V,
VSENSE = 0.0 V (during detection)
Ta = 40C
3.0
2.0
1.0 Ta = 85C Ta = 25C
0.0
0.0 2.0 4.0 6.0 8.0 10.0
VDD [V]
11. Pch transistor output current (IOUT) vs. Power supply voltage (VDD)
S-1004Cx12
VDS = 0.5 V,
VSENSE = VDET(S) + 1.0 V (during release)
5.0
4.0 Ta = 40C
3.0
2.0
Ta = 25C
1.0 Ta = 85C
0.0
0.0 2.0 4.0 6.0 8.0 10.0
VDD [V]
12. Minimum operation voltage (VOUT) vs. Power supply voltage (VDD)
S-1004Nx10
VSENSE = VDD,
S-1004Nx10
VSENSE = VDD,
Pull-up to VDD, Pull-up resistance: 100 kΩ
1.8
Pull-up to 10 V, Pull-up resistance: 100 kΩ
12.0
1.6
1.4
1.2
1.0
0.8
0.6
Ta = 40C Ta = 25C
10.0
8.0
Ta = 40C
Ta = 25C
6.0
4.0
Ta = 85C
0.4
0.2
Ta = 85C
2.0
0.0 0.0
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6
VDD [V]
VDD [V]
13. Minimum operation voltage (VOUT) vs. SENSE pin input voltage (VSENSE)
S-1004Nx10
VDD = 0.95 V,
Pull-up to VDD, Pull-up resistance: 100 kΩ
1.8
1.6
1.4
1.2
1.0
0.8 Ta = 40C
0.6
0.4
Ta = 85C
Ta = 25C
0.2
0.0
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6
S-1004Nx10
VDD = 0.95 V,
Pull-up to 10 V, Pull-up resistance: 100 kΩ
12.0
10.0
8.0 Ta = 40C
6.0
4.0
Ta = 85C
Ta = 25C
2.0
0.0
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6
VSENSE [V]
VSENSE [V]
Remark VDS: Drain-to-source voltage of the output transistor
28 Seiko Instruments Inc.


S-1004 Datasheet PDF
No Preview Available !

Click to Download PDF File for PC

BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR WITH SENSE PIN
Rev.2.1_00
S-1004 Series
14. Dynamic response vs. Output pin capacitance (COUT) (CD pin; open)
S-1004Cx10
1
Ta = +25°C,
VDD = VDET(S) + 1.0 V
S-1004Cx24
1
0.1 tPLH
0.1
Ta = +25°C,
VDD = VDET(S) + 1.0 V
tPLH
0.01
tPHL
0.001
0.00001 0.0001 0.001 0.01
Output pin capacitance [F]
0.1
S-1004Cx50
1
0.1
Ta = +25°C,
VDD = VDET(S) + 1.0 V
tPLH
0.01
tPHL
0.001
0.00001 0.0001 0.001 0.01
Output pin capacitance [F]
0.1
0.01
tPHL
0.001
0.00001 0.0001 0.001
0.01
Output pin capacitance [F]
0.1
S-1004Nx10
100
Ta = +25°C,
VDD = VDET(S) + 1.0 V
10
tPLH
1
tPHL
0.1
0.01
0.00001 0.0001 0.001
0.01
Output pin capacitance [F]
0.1
S-1004Nx50
100
Ta = +25°C,
VDD = VDET(S) + 1.0 V
10
tPLH
1
0.1 tPHL
0.01
0.00001 0.0001 0.001
0.01
Output pin capacitance [F]
0.1
S-1004Nx24
100
Ta = +25°C,
VDD = VDET(S) + 1.0 V
10
tPLH
1
tPHL
0.1
0.01
0.00001 0.0001 0.001
0.01
Output pin capacitance [F]
0.1
Seiko Instruments Inc.
29


S-1004 Datasheet PDF
No Preview Available !

Click to Download PDF File for PC

BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR WITH SENSE PIN
S-1004 Series
Rev.2.1_00
VIH*1
SENSE pin voltage
VIL*2
VDD
Output voltage
VDD 10%
1 s
tPHL
1 s
tPLH
VDD 90%
*1. VIH = 10 V
*2. VIL = 0.95 V
Figure 33 Test Condition of Response Time
VDD
P.G.
VDD
SENSE OUT
VSS CD
R
100 kΩ
Oscilloscope
VDD
P.G.
VDD
SENSE OUT
VSS CD
Oscilloscope
Figure 34 Test Circuit of Response Time
(Nch open-drain output product)
Figure 35 Test Circuit of Response Time
(CMOS output product)
Caution The above connection diagram and constant will not guarantee successful operation.
Perform thorough evaluation using the actual application to set the constant.
30 Seiko Instruments Inc.




Click to Download PDF File for PC





HOME