Seiko Instruments Electronic Components Datasheet


S-1003

HIGH-ACCURACY VOLTAGE DETECTOR


S-1003 Datasheet PDF
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S-1003 Series
www.sii-ic.com
© Seiko Instruments Inc., 2013
MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING)
HIGH-ACCURACY VOLTAGE DETECTOR
Rev.1.0_00
The S-1003 Series is a high-accuracy voltage detector developed using CMOS technology. The detection voltage is fixed
internally with an accuracy of ±1.0% (VDET 2.2 V). It operates with current consumption of 500 nA typ.
The release signal can be delayed by setting a capacitor externally. Delay time accuracy is ±15%.
Moreover, since the S-1003 Series includes the manual reset function, the reset signal can be also output forcibly.
Two output forms Nch open-drain output and CMOS output are available.
„ Features
Detection voltage:
Detection voltage accuracy:
Current consumption:
Operation voltage range:
Hysteresis width:
Manual reset function:
Delay time accuracy:
Output form:
Operation temperature range:
Lead-free (Sn 100%), halogen-free
1.2 V to 5.0 V (0.1 V step)
±1.0% (2.2 V ≤ −VDET 5.0 V)
±22 mV (1.2 V ≤ −VDET < 2.2 V)
500 nA typ.
0.95 V to 10.0 V
5% ± 2%
MR pin logic active "L", active "H"
±15% (CD = 4.7 nF)
Nch open-drain output (Active "L")
CMOS output (Active "L")
Ta = 40°C to +85°C
„ Applications
Power supply monitor for microcomputer and reset for CPU
Constant voltage power supply monitor for TV, Blu-ray recorder and home appliance
Power supply monitor for portable devices such as notebook PC, digital still camera and mobile phone
„ Packages
SOT-23-5
SNT-6A
Seiko Instruments Inc.
1


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MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) HIGH-ACCURACY VOLTAGE DETECTOR
S-1003 Series
Rev.1.0_00
„ Block Diagrams
1. Nch open-drain output product (S-1003NAxxI)
VDD
*1
VREF
+
VSS
*1
Delay
circuit
MR
*1 circuit
*1
OUT
*1
Function
Status
Output logic Active "L"
MR pin logic Active "L"
MR CD
*1. Parasitic diode
Figure 1
2. Nch open-drain output product (S-1003NBxxI)
VDD
*1
VREF
+
VSS
*1
Delay
circuit
MR
circuit
*1
*1
OUT
*1
Function
Status
Output logic Active "L"
MR pin logic Active "H"
MR CD
*1. Parasitic diode
Figure 2
2 Seiko Instruments Inc.


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MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) HIGH-ACCURACY VOLTAGE DETECTOR
Rev.1.0_00
S-1003 Series
3. CMOS output product (S-1003CAxxI)
VDD
*1
VREF
+
VSS
*1. Parasitic diode
*1
Delay
circuit
MR
circuit
*1
*1
MR CD
Figure 3
Function
Status
Output logic Active "L"
*1 MR pin logic Active "L"
OUT
*1
4. CMOS output product (S-1003CBxxI)
VDD
*1
VREF
+
VSS
*1. Parasitic diode
*1
Delay
circuit
MR
circuit
*1
*1
MR CD
Figure 4
Function
Status
Output logic Active "L"
*1 MR pin logic Active "H"
OUT
*1
Seiko Instruments Inc.
3


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MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) HIGH-ACCURACY VOLTAGE DETECTOR
S-1003 Series
Rev.1.0_00
„ Product Name Structure
Users can select the output form, MR pin logic, detection voltage value, and package type for the S-1003 Series. Refer
to "1. Product name" regarding the contents of product name, "2. Product type list" regarding the product types,
"3. Packages" regarding the package drawings and "4. Product name list" regarding details of product name.
1. Product name
S-1003 x x xx I - xxxx U
Environmental code
U: Lead-free (Sn 100%), halogen-free
Package abbreviation and IC packing specifications*1
M5T1: SOT-23-5, Tape
I6T1: SNT-6A, Tape
Operation temperature
I: Ta = 40°C to +85°C
Detection voltage value
12 to 50
(e.g., when the detection voltage is 1.2 V, it is expressed as 12.)
MR pin logic*2
A: Active "L"
B: Active "H"
Output form*2
N: Nch open-drain output (Active "L")*3
C: CMOS output (Active "L")*3
*1. Refer to the tape drawing.
*2. Refer to "2. Product type list".
*3. If you request the product with output logic active "H", contact our sales office.
2. Product type list
Product Type
NA
NB
CA
CB
Table 1
Output Form
Nch open-drain output
CMOS output
MR Pin Logic
Active "L"
Active "H"
Active "L"
Active "H"
Output Logic
Active "L"
Active "L"
Active "L"
Active "L"
3. Packages
Package Name
SOT-23-5
SNT-6A
Table 2 Package Drawing Codes
Dimension
MP005-A-P-SD
PG006-A-P-SD
Tape
MP005-A-C-SD
PG006-A-C-SD
Reel
MP005-A-R-SD
PG006-A-R-SD
Land
PG006-A-L-SD
4 Seiko Instruments Inc.


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MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) HIGH-ACCURACY VOLTAGE DETECTOR
Rev.1.0_00
S-1003 Series
4. Product name list
4. 1 S-1003 Series NA type
Output form: Nch open-drain output (Active "L")
MR pin logic: Active "L"
Detection Voltage
1.2 V ± 22 mV
1.3 V ± 22 mV
1.4 V ± 22 mV
1.5 V ± 22 mV
1.6 V ± 22 mV
1.7 V ± 22 mV
1.8 V ± 22 mV
1.9 V ± 22 mV
2.0 V ± 22 mV
2.1 V ± 22 mV
2.2 V ± 1.0%
2.3 V ± 1.0%
2.4 V ± 1.0%
2.5 V ± 1.0%
2.6 V ± 1.0%
2.7 V ± 1.0%
2.8 V ± 1.0%
2.9 V ± 1.0%
3.0 V ± 1.0%
3.1 V ± 1.0%
3.2 V ± 1.0%
3.3 V ± 1.0%
3.4 V ± 1.0%
3.5 V ± 1.0%
3.6 V ± 1.0%
3.7 V ± 1.0%
3.8 V ± 1.0%
3.9 V ± 1.0%
4.0 V ± 1.0%
4.1 V ± 1.0%
4.2 V ± 1.0%
4.3 V ± 1.0%
4.4 V ± 1.0%
4.5 V ± 1.0%
4.6 V ± 1.0%
4.7 V ± 1.0%
4.8 V ± 1.0%
4.9 V ± 1.0%
5.0 V ± 1.0%
Table 3
SOT-23-5
S-1003NA12I-M5T1U
S-1003NA13I-M5T1U
S-1003NA14I-M5T1U
S-1003NA15I-M5T1U
S-1003NA16I-M5T1U
S-1003NA17I-M5T1U
S-1003NA18I-M5T1U
S-1003NA19I-M5T1U
S-1003NA20I-M5T1U
S-1003NA21I-M5T1U
S-1003NA22I-M5T1U
S-1003NA23I-M5T1U
S-1003NA24I-M5T1U
S-1003NA25I-M5T1U
S-1003NA26I-M5T1U
S-1003NA27I-M5T1U
S-1003NA28I-M5T1U
S-1003NA29I-M5T1U
S-1003NA30I-M5T1U
S-1003NA31I-M5T1U
S-1003NA32I-M5T1U
S-1003NA33I-M5T1U
S-1003NA34I-M5T1U
S-1003NA35I-M5T1U
S-1003NA36I-M5T1U
S-1003NA37I-M5T1U
S-1003NA38I-M5T1U
S-1003NA39I-M5T1U
S-1003NA40I-M5T1U
S-1003NA41I-M5T1U
S-1003NA42I-M5T1U
S-1003NA43I-M5T1U
S-1003NA44I-M5T1U
S-1003NA45I-M5T1U
S-1003NA46I-M5T1U
S-1003NA47I-M5T1U
S-1003NA48I-M5T1U
S-1003NA49I-M5T1U
S-1003NA50I-M5T1U
SNT-6A
S-1003NA12I-I6T1U
S-1003NA13I-I6T1U
S-1003NA14I-I6T1U
S-1003NA15I-I6T1U
S-1003NA16I-I6T1U
S-1003NA17I-I6T1U
S-1003NA18I-I6T1U
S-1003NA19I-I6T1U
S-1003NA20I-I6T1U
S-1003NA21I-I6T1U
S-1003NA22I-I6T1U
S-1003NA23I-I6T1U
S-1003NA24I-I6T1U
S-1003NA25I-I6T1U
S-1003NA26I-I6T1U
S-1003NA27I-I6T1U
S-1003NA28I-I6T1U
S-1003NA29I-I6T1U
S-1003NA30I-I6T1U
S-1003NA31I-I6T1U
S-1003NA32I-I6T1U
S-1003NA33I-I6T1U
S-1003NA34I-I6T1U
S-1003NA35I-I6T1U
S-1003NA36I-I6T1U
S-1003NA37I-I6T1U
S-1003NA38I-I6T1U
S-1003NA39I-I6T1U
S-1003NA40I-I6T1U
S-1003NA41I-I6T1U
S-1003NA42I-I6T1U
S-1003NA43I-I6T1U
S-1003NA44I-I6T1U
S-1003NA45I-I6T1U
S-1003NA46I-I6T1U
S-1003NA47I-I6T1U
S-1003NA48I-I6T1U
S-1003NA49I-I6T1U
S-1003NA50I-I6T1U
Seiko Instruments Inc.
5


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MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) HIGH-ACCURACY VOLTAGE DETECTOR
S-1003 Series
Rev.1.0_00
4. 2 S-1003 Series NB type
Output form: Nch open-drain output (Active "L")
MR pin logic: Active "H"
Detection Voltage
1.2 V ± 22 mV
1.3 V ± 22 mV
1.4 V ± 22 mV
1.5 V ± 22 mV
1.6 V ± 22 mV
1.7 V ± 22 mV
1.8 V ± 22 mV
1.9 V ± 22 mV
2.0 V ± 22 mV
2.1 V ± 22 mV
2.2 V ± 1.0%
2.3 V ± 1.0%
2.4 V ± 1.0%
2.5 V ± 1.0%
2.6 V ± 1.0%
2.7 V ± 1.0%
2.8 V ± 1.0%
2.9 V ± 1.0%
3.0 V ± 1.0%
3.1 V ± 1.0%
3.2 V ± 1.0%
3.3 V ± 1.0%
3.4 V ± 1.0%
3.5 V ± 1.0%
3.6 V ± 1.0%
3.7 V ± 1.0%
3.8 V ± 1.0%
3.9 V ± 1.0%
4.0 V ± 1.0%
4.1 V ± 1.0%
4.2 V ± 1.0%
4.3 V ± 1.0%
4.4 V ± 1.0%
4.5 V ± 1.0%
4.6 V ± 1.0%
4.7 V ± 1.0%
4.8 V ± 1.0%
4.9 V ± 1.0%
5.0 V ± 1.0%
Table 4
SOT-23-5
S-1003NB12I-M5T1U
S-1003NB13I-M5T1U
S-1003NB14I-M5T1U
S-1003NB15I-M5T1U
S-1003NB16I-M5T1U
S-1003NB17I-M5T1U
S-1003NB18I-M5T1U
S-1003NB19I-M5T1U
S-1003NB20I-M5T1U
S-1003NB21I-M5T1U
S-1003NB22I-M5T1U
S-1003NB23I-M5T1U
S-1003NB24I-M5T1U
S-1003NB25I-M5T1U
S-1003NB26I-M5T1U
S-1003NB27I-M5T1U
S-1003NB28I-M5T1U
S-1003NB29I-M5T1U
S-1003NB30I-M5T1U
S-1003NB31I-M5T1U
S-1003NB32I-M5T1U
S-1003NB33I-M5T1U
S-1003NB34I-M5T1U
S-1003NB35I-M5T1U
S-1003NB36I-M5T1U
S-1003NB37I-M5T1U
S-1003NB38I-M5T1U
S-1003NB39I-M5T1U
S-1003NB40I-M5T1U
S-1003NB41I-M5T1U
S-1003NB42I-M5T1U
S-1003NB43I-M5T1U
S-1003NB44I-M5T1U
S-1003NB45I-M5T1U
S-1003NB46I-M5T1U
S-1003NB47I-M5T1U
S-1003NB48I-M5T1U
S-1003NB49I-M5T1U
S-1003NB50I-M5T1U
SNT-6A
S-1003NB12I-I6T1U
S-1003NB13I-I6T1U
S-1003NB14I-I6T1U
S-1003NB15I-I6T1U
S-1003NB16I-I6T1U
S-1003NB17I-I6T1U
S-1003NB18I-I6T1U
S-1003NB19I-I6T1U
S-1003NB20I-I6T1U
S-1003NB21I-I6T1U
S-1003NB22I-I6T1U
S-1003NB23I-I6T1U
S-1003NB24I-I6T1U
S-1003NB25I-I6T1U
S-1003NB26I-I6T1U
S-1003NB27I-I6T1U
S-1003NB28I-I6T1U
S-1003NB29I-I6T1U
S-1003NB30I-I6T1U
S-1003NB31I-I6T1U
S-1003NB32I-I6T1U
S-1003NB33I-I6T1U
S-1003NB34I-I6T1U
S-1003NB35I-I6T1U
S-1003NB36I-I6T1U
S-1003NB37I-I6T1U
S-1003NB38I-I6T1U
S-1003NB39I-I6T1U
S-1003NB40I-I6T1U
S-1003NB41I-I6T1U
S-1003NB42I-I6T1U
S-1003NB43I-I6T1U
S-1003NB44I-I6T1U
S-1003NB45I-I6T1U
S-1003NB46I-I6T1U
S-1003NB47I-I6T1U
S-1003NB48I-I6T1U
S-1003NB49I-I6T1U
S-1003NB50I-I6T1U
6 Seiko Instruments Inc.


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MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) HIGH-ACCURACY VOLTAGE DETECTOR
Rev.1.0_00
S-1003 Series
4. 3 S-1003 Series CA type
Output form: CMOS output (Active "L")
MR pin logic: Active "L"
Detection Voltage
1.2 V ± 22 mV
1.3 V ± 22 mV
1.4 V ± 22 mV
1.5 V ± 22 mV
1.6 V ± 22 mV
1.7 V ± 22 mV
1.8 V ± 22 mV
1.9 V ± 22 mV
2.0 V ± 22 mV
2.1 V ± 22 mV
2.2 V ± 1.0%
2.3 V ± 1.0%
2.4 V ± 1.0%
2.5 V ± 1.0%
2.6 V ± 1.0%
2.7 V ± 1.0%
2.8 V ± 1.0%
2.9 V ± 1.0%
3.0 V ± 1.0%
3.1 V ± 1.0%
3.2 V ± 1.0%
3.3 V ± 1.0%
3.4 V ± 1.0%
3.5 V ± 1.0%
3.6 V ± 1.0%
3.7 V ± 1.0%
3.8 V ± 1.0%
3.9 V ± 1.0%
4.0 V ± 1.0%
4.1 V ± 1.0%
4.2 V ± 1.0%
4.3 V ± 1.0%
4.4 V ± 1.0%
4.5 V ± 1.0%
4.6 V ± 1.0%
4.7 V ± 1.0%
4.8 V ± 1.0%
4.9 V ± 1.0%
5.0 V ± 1.0%
Table 5
SOT-23-5
S-1003CA12I-M5T1U
S-1003CA13I-M5T1U
S-1003CA14I-M5T1U
S-1003CA15I-M5T1U
S-1003CA16I-M5T1U
S-1003CA17I-M5T1U
S-1003CA18I-M5T1U
S-1003CA19I-M5T1U
S-1003CA20I-M5T1U
S-1003CA21I-M5T1U
S-1003CA22I-M5T1U
S-1003CA23I-M5T1U
S-1003CA24I-M5T1U
S-1003CA25I-M5T1U
S-1003CA26I-M5T1U
S-1003CA27I-M5T1U
S-1003CA28I-M5T1U
S-1003CA29I-M5T1U
S-1003CA30I-M5T1U
S-1003CA31I-M5T1U
S-1003CA32I-M5T1U
S-1003CA33I-M5T1U
S-1003CA34I-M5T1U
S-1003CA35I-M5T1U
S-1003CA36I-M5T1U
S-1003CA37I-M5T1U
S-1003CA38I-M5T1U
S-1003CA39I-M5T1U
S-1003CA40I-M5T1U
S-1003CA41I-M5T1U
S-1003CA42I-M5T1U
S-1003CA43I-M5T1U
S-1003CA44I-M5T1U
S-1003CA45I-M5T1U
S-1003CA46I-M5T1U
S-1003CA47I-M5T1U
S-1003CA48I-M5T1U
S-1003CA49I-M5T1U
S-1003CA50I-M5T1U
SNT-6A
S-1003CA12I-I6T1U
S-1003CA13I-I6T1U
S-1003CA14I-I6T1U
S-1003CA15I-I6T1U
S-1003CA16I-I6T1U
S-1003CA17I-I6T1U
S-1003CA18I-I6T1U
S-1003CA19I-I6T1U
S-1003CA20I-I6T1U
S-1003CA21I-I6T1U
S-1003CA22I-I6T1U
S-1003CA23I-I6T1U
S-1003CA24I-I6T1U
S-1003CA25I-I6T1U
S-1003CA26I-I6T1U
S-1003CA27I-I6T1U
S-1003CA28I-I6T1U
S-1003CA29I-I6T1U
S-1003CA30I-I6T1U
S-1003CA31I-I6T1U
S-1003CA32I-I6T1U
S-1003CA33I-I6T1U
S-1003CA34I-I6T1U
S-1003CA35I-I6T1U
S-1003CA36I-I6T1U
S-1003CA37I-I6T1U
S-1003CA38I-I6T1U
S-1003CA39I-I6T1U
S-1003CA40I-I6T1U
S-1003CA41I-I6T1U
S-1003CA42I-I6T1U
S-1003CA43I-I6T1U
S-1003CA44I-I6T1U
S-1003CA45I-I6T1U
S-1003CA46I-I6T1U
S-1003CA47I-I6T1U
S-1003CA48I-I6T1U
S-1003CA49I-I6T1U
S-1003CA50I-I6T1U
Seiko Instruments Inc.
7


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MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) HIGH-ACCURACY VOLTAGE DETECTOR
S-1003 Series
Rev.1.0_00
4. 4 S-1003 Series CB type
Output form: CMOS output (Active "L")
MR pin logic: Active "H"
Detection Voltage
1.2 V ± 22 mV
1.3 V ± 22 mV
1.4 V ± 22 mV
1.5 V ± 22 mV
1.6 V ± 22 mV
1.7 V ± 22 mV
1.8 V ± 22 mV
1.9 V ± 22 mV
2.0 V ± 22 mV
2.1 V ± 22 mV
2.2 V ± 1.0%
2.3 V ± 1.0%
2.4 V ± 1.0%
2.5 V ± 1.0%
2.6 V ± 1.0%
2.7 V ± 1.0%
2.8 V ± 1.0%
2.9 V ± 1.0%
3.0 V ± 1.0%
3.1 V ± 1.0%
3.2 V ± 1.0%
3.3 V ± 1.0%
3.4 V ± 1.0%
3.5 V ± 1.0%
3.6 V ± 1.0%
3.7 V ± 1.0%
3.8 V ± 1.0%
3.9 V ± 1.0%
4.0 V ± 1.0%
4.1 V ± 1.0%
4.2 V ± 1.0%
4.3 V ± 1.0%
4.4 V ± 1.0%
4.5 V ± 1.0%
4.6 V ± 1.0%
4.7 V ± 1.0%
4.8 V ± 1.0%
4.9 V ± 1.0%
5.0 V ± 1.0%
Table 6
SOT-23-5
S-1003CB12I-M5T1U
S-1003CB13I-M5T1U
S-1003CB14I-M5T1U
S-1003CB15I-M5T1U
S-1003CB16I-M5T1U
S-1003CB17I-M5T1U
S-1003CB18I-M5T1U
S-1003CB19I-M5T1U
S-1003CB20I-M5T1U
S-1003CB21I-M5T1U
S-1003CB22I-M5T1U
S-1003CB23I-M5T1U
S-1003CB24I-M5T1U
S-1003CB25I-M5T1U
S-1003CB26I-M5T1U
S-1003CB27I-M5T1U
S-1003CB28I-M5T1U
S-1003CB29I-M5T1U
S-1003CB30I-M5T1U
S-1003CB31I-M5T1U
S-1003CB32I-M5T1U
S-1003CB33I-M5T1U
S-1003CB34I-M5T1U
S-1003CB35I-M5T1U
S-1003CB36I-M5T1U
S-1003CB37I-M5T1U
S-1003CB38I-M5T1U
S-1003CB39I-M5T1U
S-1003CB40I-M5T1U
S-1003CB41I-M5T1U
S-1003CB42I-M5T1U
S-1003CB43I-M5T1U
S-1003CB44I-M5T1U
S-1003CB45I-M5T1U
S-1003CB46I-M5T1U
S-1003CB47I-M5T1U
S-1003CB48I-M5T1U
S-1003CB49I-M5T1U
S-1003CB50I-M5T1U
SNT-6A
S-1003CB12I-I6T1U
S-1003CB13I-I6T1U
S-1003CB14I-I6T1U
S-1003CB15I-I6T1U
S-1003CB16I-I6T1U
S-1003CB17I-I6T1U
S-1003CB18I-I6T1U
S-1003CB19I-I6T1U
S-1003CB20I-I6T1U
S-1003CB21I-I6T1U
S-1003CB22I-I6T1U
S-1003CB23I-I6T1U
S-1003CB24I-I6T1U
S-1003CB25I-I6T1U
S-1003CB26I-I6T1U
S-1003CB27I-I6T1U
S-1003CB28I-I6T1U
S-1003CB29I-I6T1U
S-1003CB30I-I6T1U
S-1003CB31I-I6T1U
S-1003CB32I-I6T1U
S-1003CB33I-I6T1U
S-1003CB34I-I6T1U
S-1003CB35I-I6T1U
S-1003CB36I-I6T1U
S-1003CB37I-I6T1U
S-1003CB38I-I6T1U
S-1003CB39I-I6T1U
S-1003CB40I-I6T1U
S-1003CB41I-I6T1U
S-1003CB42I-I6T1U
S-1003CB43I-I6T1U
S-1003CB44I-I6T1U
S-1003CB45I-I6T1U
S-1003CB46I-I6T1U
S-1003CB47I-I6T1U
S-1003CB48I-I6T1U
S-1003CB49I-I6T1U
S-1003CB50I-I6T1U
8 Seiko Instruments Inc.


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MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) HIGH-ACCURACY VOLTAGE DETECTOR
Rev.1.0_00
S-1003 Series
„ Pin Configurations
1. SOT-23-5
Top view
54
123
Figure 5
Pin No.
1
2
3
4
5
Symbol
CD
VSS
MR
OUT
VDD
Table 7
Description
Connection pin for delay capacitor
GND pin
Manual reset pin
Voltage detection output pin
Voltage input pin
2. SNT-6A
Top view
16
25
34
Figure 6
Table 8
Pin No.
Symbol
Description
1 CD
Connection pin for delay capacitor
2 VDD
Voltage input pin
3 OUT
Voltage detection output pin
4 MR
5 NC*1
Manual reset pin
No connection
6 VSS
GND pin
*1. The NC pin is electrically open.
The NC pin can be connected to the VDD pin or the VSS pin.
Seiko Instruments Inc.
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MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) HIGH-ACCURACY VOLTAGE DETECTOR
S-1003 Series
Rev.1.0_00
„ Absolute Maximum Ratings
Table 9
Item Symbol
Power supply voltage
CD pin input voltage
MR pin input voltage
Output voltage
Nch open-drain output product
CMOS output product
VDD VSS
VCD
VMR
VOUT
Output current
Power dissipation
SOT-23-5
SNT-6A
IOUT
PD
Operation ambient temperature
Topr
Storage temperature
Tstg
*1. When mounted on board
[Mounted board]
(1) Board size: 114.3 mm × 76.2 mm × t1.6 mm
(2) Name:
JEDEC STANDARD51-7
(Ta = +25°C unless otherwise specified)
Absolute Maximum Rating
Unit
12.0 V
VSS 0.3 to VDD + 0.3
VSS 0.3 to VDD + 0.3
VSS 0.3 to 12.0
VSS 0.3 to VDD + 0.3
50
600*1
400*1
V
V
V
V
mA
mW
mW
40 to +85
40 to +125
°C
°C
Caution The absolute maximum ratings are rated values exceeding which the product could suffer
physical damage. These values must therefore not be exceeded under any conditions.
700
600
500 SOT-23-5
400
300
200 SNT-6A
100
0
0 50 100 150
Ambient Temperature (Ta) [°C]
Figure 7 Power Dissipation of Package (When Mounted on Board)
10 Seiko Instruments Inc.


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MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) HIGH-ACCURACY VOLTAGE DETECTOR
Rev.1.0_00
S-1003 Series
„ Electrical Characteristics
1. Nch open-drain output product
Table 10
(Ta = +25°C unless otherwise specified)
Item Symbol
Condition
Min.
Typ.
Max.
Unit
Test
Circuit
Detection voltage*1
VDET
1.2 V ≤ −VDET < 2.2 V
2.2 V ≤ −VDET 5.0 V
VDET(S)
0.022
VDET(S)
× 0.99
VDET(S)
VDET(S)
VDET(S)
+ 0.022
VDET(S)
× 1.01
V
V
1
1
Hysteresis width
VHYS
VDET
× 0.03
VDET
× 0.05
VDET
× 0.07
V
1
Current consumption ISS
Operation voltage
VDD
Output current
IOUT
VDD = VDET(S) + 1.0 V
Output transistor
VDD = 0.95 V
Nch
VDS*2 = 0.5 V
MR pin active
VDD = 1.2 V
VDD = 2.4 V
VDD = 4.8 V
Output transistor
0.50 0.90 μA 2
0.95 10.0 V 1
0.59 1.00 mA 3
0.73 1.33 mA 3
1.47 2.39 mA 3
1.86 2.50 mA 3
Leakage current
Delay time*3
Detection voltage
temperature
coefficient*4
ILEAK
tD
Nch
VDD = 10.0 V, VOUT = 10.0 V
MR pin non-active
CD = 4.7 nF
Δ−VDET
ΔTa • −VDET
Ta = 40°C to +85°C
− − 0.08 μA 3
8.5 10.0 11.5 ms 4
− ±100 ±350 ppm/°C 1
MR pin
input voltage "H"
VMRH
NA type
(MR pin logic active "L")
NB type
(MR pin logic active "H")
VDD
0.3
1.2
V6
V6
MR pin
input voltage "L"
VMRL
NA type
(MR pin logic active "L")
NB type
(MR pin logic active "H")
VDD
1.2
V
6
− − 0.3 V 6
MR pin
input resistance
RMR
0.5 1.0 1.6 MΩ 6
*1. VDET: Actual detection voltage value, VDET(S): Set detection voltage value (the center value of the detection voltage
range in Table 3 or Table 4.)
*2. VDS: Drain-to-source voltage of the output transistor
*3. The time period from when the pulse voltage of 0.95 V → −VDET(S) + 1.0 V is applied to the VDD pin to when VOUT
reaches VDD × 0.9, after the output pin is pulled up to VDD by the resistance of 100 kΩ.
*4. The temperature change of the detection voltage [mV/°C] is calculated by using the following equation.
Δ − VDET
ΔTa
[mV/°C]*1 = VDET(S) (typ.)[V]*2 ×
Δ − VDET
ΔTa • −VDET
[ppm/°C]*3 ÷ 1000
*1. Temperature change of the detection voltage
*2. Set detection voltage
*3. Detection voltage temperature coefficient
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MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) HIGH-ACCURACY VOLTAGE DETECTOR
S-1003 Series
Rev.1.0_00
2. CMOS output product
Table 11
(Ta = +25°C unless otherwise specified)
Item Symbol
Condition
Min.
Typ.
Max.
Unit
Test
Circuit
Detection voltage*1
VDET
1.2 V ≤ −VDET < 2.2 V
2.2 V ≤ −VDET 5.0 V
VDET(S)
0.022
VDET(S)
× 0.99
VDET(S)
VDET(S)
VDET(S)
+ 0.022
VDET(S)
× 1.01
V
V
1
1
Hysteresis width
VHYS
VDET
× 0.03
VDET
× 0.05
VDET
× 0.07
V
1
Current consumption ISS
Operation voltage
VDD
Output current
IOUT
VDD = VDET(S) + 1.0 V
0.50 0.90 μA 2
0.95 10.0 V 1
Output transistor VDD = 0.95 V
0.59 1.00 mA 3
Nch
VDS*2 = 0.5 V
MR pin active
VDD = 1.2 V
VDD = 2.4 V
VDD = 4.8 V
0.73 1.33 mA 3
1.47 2.39 mA 3
1.86 2.50 mA 3
Output transistor
Pch
VDD = 4.8 V
S-1003Cx12 to 43
1.62
2.60
mA 5
VDS*2 = 0.5 V
VDD = 6.0 V
1.78 2.86 mA 5
Delay time*3
Detection voltage
temperature
coefficient*4
tD CD = 4.7 nF
Δ−VDET
ΔTa • −VDET
Ta = 40°C to +85°C
8.5 10.0 11.5 ms 4
− ±100 ±350 ppm/°C 1
MR pin
input voltage "H"
VMRH
CA type
(MR pin logic active "L")
CB type
(MR pin logic active "H")
VDD
0.3
1.2
V6
V6
MR pin
input voltage "L"
VMRL
CA type
(MR pin logic active "L")
CB type
(MR pin logic active "H")
VDD
1.2
V
6
− − 0.3 V 6
MR pin
input resistance
RMR
0.5 1.0 1.6 MΩ 6
*1. VDET: Actual detection voltage value, VDET(S): Set detection voltage value (the center value of the detection voltage
range in Table 5 or Table 6.)
*2. VDS: Drain-to-source voltage of the output transistor
*3. The time period from when the pulse voltage of 0.95 V → −VDET(S) + 1.0 V is applied to the VDD pin to when VOUT
reaches VDD × 0.9.
*4. The temperature change of the detection voltage [mV/°C] is calculated by using the following equation.
Δ − VDET
ΔTa
[mV/°C]*1 = VDET(S) (typ.)[V]*2 ×
Δ − VDET
ΔTa • −VDET
[ppm/°C]*3 ÷ 1000
*1. Temperature change of the detection voltage
*2. Set detection voltage
*3. Detection voltage temperature coefficient
12 Seiko Instruments Inc.


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MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) HIGH-ACCURACY VOLTAGE DETECTOR
Rev.1.0_00
S-1003 Series
„ Test Circuits
VDD
VDD
+
V MR OUT
*2 VSS CD
R*1
100 kΩ
+
V
+A
VDD VDD
MR OUT
*1 VSS CD
*1. R is unnecessary for CMOS output product.
*2. Set to VDD or GND (MR pin non-active).
Figure 8 Test Circuit 1
*1. Set to VDD or GND (MR pin non-active).
Figure 9 Test Circuit 2
VDD
VDD +
V MR OUT
VSS CD
*1
+
A
+
V
VDS
P.G.
VDD
MR
*2 VSS
OUT
CD
CD
Oscilloscope
R*1
100 kΩ
VOUT
*1. Set to VDD or GND.
Figure 10 Test Circuit 3
*1. R is unnecessary for CMOS output product.
*2. Set to VDD or GND (MR pin non-active).
Figure 11 Test Circuit 4
VDD
VDD +
V MR OUT
VSS CD
*1
+
V
+
A
VDS
VDD VDD
+
A MR OUT
VMR + VSS CD
V
R*1
100 kΩ
+
V
*1. Set to VDD or GND (MR pin non-active).
Figure 12 Test Circuit 5
*1. R is unnecessary for CMOS output product.
Figure 13 Test Circuit 6
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MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) HIGH-ACCURACY VOLTAGE DETECTOR
S-1003 Series
Rev.1.0_00
„ Timing Charts
1. Nch open-drain output product
Hysteresis width
(VHYS)
VDD
VDD
Release voltage (+VDET)
Detection voltage (VDET)
Minimum operation voltage
VSS
VDD
Output from OUT pin
VDD
MR OUT
*1 VSS CD
R
100 kΩ
+
V
VSS
tD
*1. Set to VDD or GND (MR pin non-active).
Figure 14
2. CMOS output product
Hysteresis width
(VHYS)
VDD
VDD
Release voltage (+VDET)
Detection voltage (VDET)
Minimum operation voltage
VSS
VDD
VDD
MR OUT
*1 VSS CD
+
V
Output from OUT pin
VSS
tD
*1. Set to VDD or GND (MR pin non-active).
Remark When VDD is the minimum operation voltage or less, the output voltage from the OUT pin is indefinite
in the shaded area.
Figure 15
14 Seiko Instruments Inc.


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MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) HIGH-ACCURACY VOLTAGE DETECTOR
Rev.1.0_00
S-1003 Series
„ Operation
1. Basic operation: CMOS output (active "L") product
(1) When the power supply voltage (VDD) is the release voltage (+VDET) or more, the Nch transistor is OFF and
the Pch transistor is ON to output VDD ("H"). Since the Nch transistor N1 in Figure 16 is OFF, the comparator
input voltage is
(RB + RC ) VDD
RA + RB + RC
.
(2) Although VDD decreases to +VDET or less, VDD is output when VDD is higher than the detection voltage (VDET).
When VDD decreases to VDET or less (point A in Figure 17), the Nch transistor is ON and the Pch transistor
is OFF so that VSS ("L") is output. At this time, the Nch transistor N1 in Figure 16 is turned on, and the input
voltage to the comparator is
RB VDD
RA + RB
.
(3) The output is indefinite by decreasing VDD to the IC's minimum operation voltage or less. If the output is
pulled up, it will be VDD.
(4) VSS is output by increasing VDD to the minimum operation voltage or more. Although VDD exceeds VDET and
VDD is less than +VDET, the output is VSS.
(5) When increasing VDD to +VDET or more (point B in Figure 17), the Nch transistor is OFF and the Pch
transistor is ON so that VDD is output. At this time, VDD is output from the OUT pin after the passage of the
delay time (tD).
VDD
VSS
RA
*1
RB
VREF
+
RC N1
*1 Pch
Delay
circuit
Nch
MR
*1 circuit
*1
*1
OUT
*1
MR CD
CD
*1. Parasitic diode
Figure 16 Operation 1
(1) (2) (3) (4)
Hysteresis width
(VHYS)
A
B
(5)
VDD
Release voltage (+VDET)
Detection voltage (VDET)
Minimum operation voltage
VSS
VDD
Output from OUT pin
VSS
Remark
tD
When VDD is the minimum operation voltage or less, the output voltage from the OUT pin is indefinite
in the shaded area.
Figure 17 Operation 2
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MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) HIGH-ACCURACY VOLTAGE DETECTOR
S-1003 Series
Rev.1.0_00
2. Manual reset function
The OUT pin voltage can be changed to detection status forcibly by the MR pin input voltage (VMR).
When not using the manual reset function, set VMR = VDD in the S-1003 Series xA type, and VMR = VSS in the
S-1003 Series xB type.
Caution
Perform thorough evaluation in the actual application when using the MR pin in open. Due to the
parasitic capacitance of the MR pin, the manual reset function may malfunction when the power supply
fluctuates.
2. 1 S-1003 Series xA type (MR pin logic active "L")
(1) MR pin = "L"
When the VDD pin voltage is the release voltage (+VDET) or more, the OUT pin changes to the detection status
from the release status immediately if a voltage of the MR pin input voltage "L" (VMRL) or less is applied to the
MR pin.
(2) MR pin = "H"
If a voltage of the MR pin input voltage "H" (VMRH) or more is applied to the MR pin, output from the OUT pin is
determined to be "H" or "L" depending on the VDD pin voltage.
After the passage of the delay time (tD), the OUT pin changes to the release status from the detection status.
Input from VDD pin
(1) (2)
VDD (≥ +VDET)
Input from MR pin
MR pin input voltage "H" (VMRH)
MR pin input voltage "L" (VMRL)
VDD
Output from OUT pin
VSS
tD
Figure 18 Timing Chart of MR Pin Logic Active "L"
Remark Since the MR pin is pulled up to the VDD pin internally, output from the OUT pin is determined to be "H" or "L" in
the floating status depending on the VDD pin voltage (Refer to Figure 19).
RMR
VDD
*1
MR
*1
VSS
*1. Parasitic diode
Figure 19
16 Seiko Instruments Inc.


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MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) HIGH-ACCURACY VOLTAGE DETECTOR
Rev.1.0_00
S-1003 Series
2. 2 S-1003 Series xB type (MR pin logic active "H")
(1) MR pin = "H"
When the VDD pin voltage is the release voltage (+VDET) or more, the OUT pin changes to the detection status
from the release status immediately if a voltage of the MR pin input voltage "H" (VMRH) or more is applied to the
MR pin.
(2) MR pin = "L"
If a voltage of the MR pin input voltage "L" (VMRL) or less is applied to the MR pin, output from the OUT pin is
determined to be "H" or "L" depending on the VDD pin voltage.
After the passage of the delay time (tD), the OUT pin changes to the release status from the detection status.
Input from VDD pin
(1) (2)
VDD (≥ +VDET)
Input from MR pin
MR pin input voltage "H" (VMRH)
MR pin input voltage "L" (VMRL)
VDD
Output from OUT pin
VSS
tD
Figure 20 Timing Chart of MR Pin Logic Active "H"
Remark Since the MR pin is pulled down to the VSS pin internally, output from the OUT pin is determined to be "H" or
"L" in the floating status depending on the VDD pin voltage (Refer to Figure 21).
VDD
*1
MR
RMR
*1
VSS
*1. Parasitic diode
Figure 21
Seiko Instruments Inc.
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MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) HIGH-ACCURACY VOLTAGE DETECTOR
S-1003 Series
Rev.1.0_00
2. 3 Cautions of manual reset function
2. 3. 1 Slew rate when switching manual reset function
Although there is a hysteresis width between the MR pin input voltage "L" (VMRL) and the MR pin input voltage "H"
(VMRH), note that the IC may malfunction if the slew rate (Refer to Figure 22, Figure 23) is low when the MR pin
voltage is changed.
The slew rate is calculated by using the following equation.
Slew rate =
VMRH VMRL
Δt
(1) When MR pin logic is active "L"
The OUT pin voltage may oscillate if the parasitic resistance (RP) between the power supply and the VDD pin is
high.
In case of RP 8 kΩ:
Connect a capacitor of 1 nF or more between the VDD pin and the VSS pin.
In case of 5 kΩ ≤ RP < 8 kΩ: Capacitors are unnecessary if the slew rate is 100 V/s or higher.
In case of RP < 5 kΩ:
Capacitors are unnecessary if the slew rate is 1 V/s or higher.
VMR
VMRH
VMRL
Time
Δt
Figure 22
(2) When MR pin logic is active "H"
Connect a capacitor of 100 pF or more to the CD pin, and set the slew rate 20 V/s or higher.
VMR
VMRH
VMRL
Δt
Figure 23
Time
18 Seiko Instruments Inc.


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MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) HIGH-ACCURACY VOLTAGE DETECTOR
Rev.1.0_00
S-1003 Series
2. 4 When connecting resistance (RA) between power supply voltage (VDD) and VDD pin
When the MR pin voltage (VMR) is an intermediate voltage (especially VMRL < VMR < VMRH), the current consumption
increases by 25 μA max. A voltage drop occurs since this current flows through RA. If the VDD pin voltage (VIN)
becomes the detection voltage (VDET) or less for that reason, the OUT pin changes to the detection status, and the
detection status or the release status are not controlled by VMR. The OUT pin may not be able to change to the
release status unless VDD is raised (Refer to Figure 24).
(1) When MR pin logic is active "L"
In case of VIN > VMR, a current also flows through the MR pin input resistance (RMR). For example, when VIN =
10 V, VMR = 1 V, RMR = 0.5 MΩ (min.), a current of 18 μA flows from the VDD pin to the MR pin. Therefore, set
RA so as to satisfy the following equation.
RA (VDD (VDET)) / (25 μA + MR pin current)
(2) When MR pin logic is active "H"
Set RA so as to satisfy the following equation.
RA (VDD (VDET)) / 25 μA
VDD
GND
RA
VIN
VDD
MR
VSS
VMR
OUT
CD
(Nch open-drain output product)
Figure 24
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MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) HIGH-ACCURACY VOLTAGE DETECTOR
S-1003 Series
Rev.1.0_00
3. Delay circuit
The delay circuit delays the output signal to the OUT pin from the time at which the power supply voltage (VDD)
exceeds the release voltage (+VDET) when VDD is turned on. The output signal is not delayed when VDD decreases
to the detection voltage (VDET) or less (refer to "Figure 17 Operation 2").
The delay time (tD) is determined by the time constant of the built-in constant current (approx. 100 nA) and the
attached delay capacitor (CD), or the delay time (tD0) when the CD pin is open, and calculated from the following
equation. When the CD value is sufficiently large, the tD0 value can be disregarded.
tD [ms] = Delay coefficient × CD [nF] + tD0 [ms]
Operation
Temperature
Ta = +85°C
Ta = +25°C
Ta = 40°C
Table 12 Delay Coefficient
Delay Coefficient
Min. Typ.
1.60 1.89
1.78 2.05
2.01 2.31
Max.
2.13
2.30
2.71
Operation Temperature
Ta = 40°C to +85°C
Table 13 Delay Time
Min.
0.021 ms
Delay Time (tD0)
Typ.
0.044 ms
Max.
0.147 ms
Caution 1.
When the CD pin is open, a double pulse shown in Figure 25 may appear at release.
To avoid the double pulse, attach a 100 pF or larger capacitor to the CD pin. Do not apply
voltage to the CD pin from the exterior.
VOUT
Figure 25
Time
2. Mounted board layout should be made in such a way that no current flows into or flows from
the CD pin since the impedance of the CD pin is high, otherwise correct delay time cannot be
provided.
3. There is no limit for the capacitance of CD as long as the leakage current of the capacitor can
be ignored against the built-in constant current value. Leakage current causes deviation in
delay time. When the leakage current is larger than the built-in constant current, no release
takes place.
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MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) HIGH-ACCURACY VOLTAGE DETECTOR
Rev.1.0_00
S-1003 Series
4. Other characteristics
4. 1 Temperature characteristics of detection voltage
The shaded area in Figure 26 shows the temperature characteristics of detection voltage in the operation
temperature range.
VDET [V]
+0.945 mV/°C
VDET25*1
0.945 mV/°C
40 +25 +85 Ta [°C]
*1. VDET25 is an actual detection voltage value at Ta = +25°C.
Figure 26 Temperature Characteristics of Detection Voltage (Example for VDET = 2.7 V)
4. 2 Temperature characteristics of release voltage
The temperature change
Δ + VDET
ΔTa
of the release voltage is calculated by using the temperature change
Δ − VDET
ΔTa
of the detection voltage as follows:
Δ + VDET
ΔTa
=
+VDET
VDET
×
Δ − VDET
ΔTa
The temperature change of the release voltage and the detection voltage has the same sign consequently.
4. 3 Temperature characteristics of hysteresis voltage
The temperature change of the hysteresis voltage is expressed as
Δ + VDET
ΔTa
Δ − VDET
ΔTa
and is calculated as
follows:
Δ + VDET
ΔTa
Δ − VDET
ΔTa
=
VHYS
VDET
×
Δ − VDET
ΔTa
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MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) HIGH-ACCURACY VOLTAGE DETECTOR
S-1003 Series
Rev.1.0_00
„ Standard Circuit
VDD
MR
VSS
OUT
CD
CD*2
R*1
100 kΩ
*1. R is unnecessary for CMOS output product.
*2. The delay capacitor (CD) should be connected directly to the CD pin and the VSS pin.
Figure 27
Caution The above connection diagram and constant will not guarantee successful operation.
Perform thorough evaluation using the actual application to set the constant.
22 Seiko Instruments Inc.


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MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) HIGH-ACCURACY VOLTAGE DETECTOR
Rev.1.0_00
S-1003 Series
„ Explanation of Terms
1. Detection voltage (VDET)
The detection voltage is a voltage at which the output in Figure 30 turns to "L". The detection voltage varies slightly
among products of the same specification. The variation of detection voltage between the specified minimum
(VDET min.) and the maximum (VDET max.) is called the detection voltage range (Refer to Figure 28).
Example: In the S-1003Cx15, the detection voltage is either one in the range of 1.478 V ≤ −VDET 1.522 V.
This means that some S-1003Cx15 have VDET = 1.478 V and some have VDET = 1.522 V.
2. Release voltage (+VDET)
The release voltage is a voltage at which the output in Figure 30 turns to "H". The release voltage varies slightly
among products of the same specification. The variation of release voltage between the specified minimum (+VDET
min.) and the maximum (+VDET max.) is called the release voltage range (Refer to Figure 29). The range is
calculated from the actual detection voltage (VDET) of a product and is in the range of VDET × 1.03 ≤ +VDET ≤ −VDET
× 1.07.
Example: For the S-1003Cx15, the release voltage is either one in the range of 1.522 V ≤ +VDET 1.629 V.
This means that some S-1003Cx15 have +VDET = 1.522 V and some have +VDET = 1.629 V.
VDD
VDET max.
VDET min.
Detection voltage
Detection voltage
range
Release voltage
+VDET max.
+VDET min.
VDD
Release voltage
range
OUT
Figure 28 Detection Voltage
OUT
tD
Figure 29 Release Voltage
VDD
VDD
+
V MR OUT
*2 VSS CD
R*1
100 kΩ
+
V
*1. R is unnecessary for CMOS output product.
*2. Set to VDD or GND (MR pin non-active).
Figure 30 Test Circuit of Detection Voltage and Release Voltage
Seiko Instruments Inc.
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MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) HIGH-ACCURACY VOLTAGE DETECTOR
S-1003 Series
Rev.1.0_00
3. Hysteresis width (VHYS)
The hysteresis width is the voltage difference between the detection voltage and the release voltage (the voltage at
point B the voltage at point A = VHYS in "Figure 17 Operation 2"). Setting the hysteresis width between the
detection voltage and the release voltage, prevents malfunction caused by noise on the input voltage.
4. Delay time (tD)
The delay time in the S-1003 Series is a period from the input voltage to the VDD pin exceeding the release voltage
(+VDET) until the output from the OUT pin inverts. The delay time changes according to the delay capacitor (CD).
VDD
+VDET
OUT
tD
Figure 31 Delay Time
5. Feed-through current
Feed-through current is a current that flows instantaneously at the time of detection and release of a voltage
detector. The feed-through current is large in CMOS output product, small in Nch open-drain output product.
6. Oscillation
In applications where a resistor is connected to the voltage detector input (Figure 32), taking a CMOS active "L"
product for example, the feed-through current which is generated when the output goes from "L" to "H" (release)
causes a voltage drop equal to [feed-through current] × [input resistance] across the resistor. When the input
voltage drops below the detection voltage (VDET) as a result, the output voltage goes to "L". In this status, the
feed-through current stops and its resultant voltage drop disappears, and the output goes from "L" to "H". The
feed-through current is then generated again, a voltage drop appears, and repeating the process finally induces
oscillation.
VDD
RA
VIN
RB
VDD
MR OUT
VSS CD
(CMOS output product)
GND
Figure 32 Example for Bad Implementation Due to Detection Voltage Change
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MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) HIGH-ACCURACY VOLTAGE DETECTOR
Rev.1.0_00
S-1003 Series
„ Precautions
Do not apply an electrostatic discharge to this IC that exceeds the performance ratings of the built-in electrostatic
protection circuit.
In CMOS output product of the S-1003 Series, the feed-through current flows at the detection and the release. If the
input impedance is high, oscillation may occur due to the voltage drop by the feed-through current when releasing.
In CMOS output product oscillation may occur when a pull-down resistor is used, and falling speed of the power
supply voltage (VDD) is slow near the detection voltage.
When designing for mass production using an application circuit described herein, the product deviation and
temperature characteristics of the external parts should be taken into consideration. SII shall not bear any
responsibility for patent infringements related to products using the circuits described herein.
SII claims no responsibility for any disputes arising out of or in connection with any infringement by products
including this IC of patents owned by a third party.
As seen in Figure 33, when connecting an input resistance (RA) in Nch open-drain output product of the S-1003
Series, RA should be 100 kΩ or less to prevent oscillation. Moreover, note that the hysteresis width may be larger
as the following equation.
Maximum hysteresis width = VHYS + RA 20 μA
When using the manual reset function, refer to "2. 4 When connecting resistance (RA) between power supply
voltage (VDD) and VDD pin" in "„ Operation" to set the constant.
VDD
RA
(RA 100 kΩ)
VIN
Set to VIN or GND (MR pin non-active)
VDD
MR OUT
VSS CD
(Nch open-drain output product)
GND
Figure 33
Caution The above connection diagram and constant will not guarantee successful operation.
Perform thorough evaluation using the actual application to set the constant.
Seiko Instruments Inc.
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MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) HIGH-ACCURACY VOLTAGE DETECTOR
S-1003 Series
Rev.1.0_00
„ Characteristics (Typical Data)
1. Detection voltage (VDET) vs. Temperature (Ta)
S-1003CA12
1.40
S-1003CA24
2.60
1.30
1.20
1.10
+VDET
VDET
2.50
2.40
2.30
1.00
40 25
0 25
Ta [°C]
50
75 85
2.20
40 25
S-1003CA50
5.40
5.20
+VDET
5.00
4.80
VDET
4.60
40 25
0 25
Ta [°C]
50
75 85
2. Hysteresis width (VHYS) vs. Temperature (Ta)
S-1003CA12
7
S-1003CA24
7
66
55
44
3
40 25
0 25
Ta [°C]
50
75 85
3
40 25
S-1003CA50
7
6
5
4
3
40 25
0 25
Ta [°C]
50
75 85
+VDET
VDET
0 25
Ta [°C]
50
0 25
Ta [°C]
50
75 85
75 85
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MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) HIGH-ACCURACY VOLTAGE DETECTOR
Rev.1.0_00
S-1003 Series
3. Current consumption (ISS) vs. Input voltage (VDD)
S-1003CA12
1.50
Ta = +25°C
S-1003CA24
1.50
1.25 1.25
1.00 1.00
0.75 0.75
0.50 0.50
0.25 0.25
0
0 2 4 6 8 10
VDD [V]
0
0
2
Ta = +25°C
46
VDD [V]
8 10
S-1003CA50
1.50
1.25
1.00
0.75
0.50
0.25
0
0
2
Ta = +25°C
46
VDD [V]
8 10
4. Current consumption (ISS) vs. Temperature (Ta)
S-1003NA12
1.00
VDD = VDET(S) + 1.0 V
S-1003NA24
1.00
0.75 0.75
0.50 0.50
VDD = VDET(S) + 1.0 V
0.25 0.25
0
40 25
0 25
Ta [°C]
50
75 85
0
40 25
0 25
Ta [°C]
50
75 85
S-1003NA50
1.00
VDD = VDET(S) + 1.0 V
0.75
0.50
0.25
0
40 25
0 25
Ta [°C]
50
75 85
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MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) HIGH-ACCURACY VOLTAGE DETECTOR
S-1003 Series
Rev.1.0_00
5. Nch transistor output current (IOUT) vs. VDS
S-1003NA12
20.0
17.5
15.0
12.5
10.0
7.5
5.0
2.5
0
0
Ta = +25°C, MR pin active
VDD = 6.00 V
VDD = 4.80 V
VDD = 3.60 V
VDD = 2.40 V
VDD = 1.20 V
VDD = 0.95 V
1.0 2.0 3.0 4.0 5.0 6.0 7.0
VDS [V]
6. Pch transistor output current (IOUT) vs. VDS
S-1003CA12
40.0
Ta = +25°C
VDD = 8.4 V
30.0
20.0
10.0
0
0
VDD = 7.2 V
VDD = 6.0 V
VDD = 4.8 V
VDD = 3.6 V
VDD = 2.4 V
2.0 4.0 6.0 8.0 10.0
VDS [V]
7. Nch transistor output current (IOUT) vs.
Input voltage (VDD)
S-1003NA12
VDS = 0.5 V, MR pin active
4.0
Ta = 40°C
3.0
2.0
1.0 Ta = +85°C Ta = +25°C
0
0 2.0 4.0 6.0 8.0 10.0
VDD [V]
8. Pch transistor output current (IOUT) vs.
Input voltage (VDD)
S-1003CA12
5.0
4.0
Ta = 40°C
VDS = 0.5 V
3.0
2.0
1.0
0
0
Ta = +25°C
Ta = +85°C
2.0 4.0 6.0 8.0 10.0
VDD [V]
Remark VDS: Drain-to-source voltage of the output transistor
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MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) HIGH-ACCURACY VOLTAGE DETECTOR
Rev.1.0_00
S-1003 Series
9. Minimum operation voltage (VOUT) vs. Input voltage (VDD)
S-1003NA12
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
0
0.2
Pull-up to VDD
Pull-up resistance: 100 kΩ
Ta = 40°C
Ta = +25°C
Ta = +85°C
0.4 0.6 0.8 1.0 1.2 1.4 1.6
VDD [V]
S-1003NA24
3.0
Pull-up to VDD
Pull-up resistance: 100 kΩ
2.5
2.0
1.5
1.0
0.5
0
0
Ta = 40°C
Ta = +25°C
Ta = +85°C
0.4 0.8 1.2 1.6 2.0 2.4 2.8
VDD [V]
S-1003NA50
6.0
Pull-up to VDD
Pull-up resistance: 100 kΩ
5.0
4.0
3.0
2.0
Ta = 40°C
1.0
Ta = +25°C
Ta = +85°C
0
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD [V]
S-1003NA12
12.0
Pull-up to 10 V
Pull-up resistance: 100 kΩ
10.0
8.0 Ta = 40°C
6.0
4.0
Ta = +25°C
Ta = +85°C
2.0
0
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6
VDD [V]
S-1003NA24
12.0
Pull-up to 10 V
Pull-up resistance: 100 kΩ
10.0
8.0 Ta = 40°C
6.0 Ta = +25°C
4.0 Ta = +85°C
2.0
0
0 0.4 0.8 1.2 1.6 2.0 2.4 2.8
VDD [V]
S-1003NA50
12.0
Pull-up to 10 V
Pull-up resistance: 100 kΩ
10.0
8.0 Ta = 40°C
6.0
Ta = +25°C
Ta = +85°C
4.0
2.0
0
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD [V]
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MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) HIGH-ACCURACY VOLTAGE DETECTOR
S-1003 Series
Rev.1.0_00
10. Dynamic response vs. Output pin capacitance (COUT) (CD pin; open)
S-1003CA12
S-1003CA24
11
0.1 tPLH
0.1 tPLH
0.01
tPHL
0.001
0.00001 0.0001 0.001 0.01
Output pin capacitance [μF]
S-1003CA50
1
0.1 tPLH
0.1
0.01
tPHL
0.001
0.00001 0.0001 0.001 0.01
Output pin capacitance [μF]
0.1
0.01
tPHL
0.001
0.00001 0.0001 0.001
0.01
Output pin capacitance [μF]
S-1003NA12
100
10
1 tPLH
0.1
0.01
0.001
0.00001
tPHL
0.0001 0.001 0.01
Output pin capacitance [μF]
S-1003NA50
100
10
1 tPLH
0.1
0.01
0.001
0.00001
tPHL
0.0001 0.001 0.01
Output pin capacitance [μF]
0.1
0.1
0.1
S-1003NA24
100
10
1 tPLH
0.1
0.01
0.001
0.00001
tPHL
0.0001 0.001 0.01
Output pin capacitance [μF]
0.1
30 Seiko Instruments Inc.




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