MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) HIGH-ACCURACY VOLTAGE DETECTOR
• Do not apply an electrostatic discharge to this IC that exceeds the performance ratings of the built-in electrostatic
• In CMOS output product of the S-1003 Series, the feed-through current flows at the detection and the release. If the
input impedance is high, oscillation may occur due to the voltage drop by the feed-through current when releasing.
• In CMOS output product oscillation may occur when a pull-down resistor is used, and falling speed of the power
supply voltage (VDD) is slow near the detection voltage.
• When designing for mass production using an application circuit described herein, the product deviation and
temperature characteristics of the external parts should be taken into consideration. SII shall not bear any
responsibility for patent infringements related to products using the circuits described herein.
• SII claims no responsibility for any disputes arising out of or in connection with any infringement by products
including this IC of patents owned by a third party.
• As seen in Figure 33, when connecting an input resistance (RA) in Nch open-drain output product of the S-1003
Series, RA should be 100 kΩ or less to prevent oscillation. Moreover, note that the hysteresis width may be larger
as the following equation.
Maximum hysteresis width = VHYS + RA • 20 μA
• When using the manual reset function, refer to "2. 4 When connecting resistance (RA) between power supply
voltage (VDD) and VDD pin" in " Operation" to set the constant.
(RA ≤ 100 kΩ)
Set to VIN or GND (MR pin non-active)
(Nch open-drain output product)
Caution The above connection diagram and constant will not guarantee successful operation.
Perform thorough evaluation using the actual application to set the constant.
Seiko Instruments Inc.