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ATmega2564/1284/644RFR2
Features
Network support by hardware assisted Multiple PAN Address Filtering
Advanced Hardware assisted Reduced Power Consumption
High Performance, Low Power AVR® 8-Bit Microcontroller
Advanced RISC Architecture
- 135 Powerful Instructions – Most Single Clock Cycle Execution
- 32x8 General Purpose Working Registers / On-Chip 2-cycle Multiplier
- Up to 16 MIPS Throughput at 16 MHz and 1.8V – Fully Static Operation
Non-volatile Program and Data Memories
- 256K/128K/64K Bytes of In-System Self-Programmable Flash
Endurance: 10’000 Write/Erase Cycles @ 125°C (25’000 Cycles @ 85°C)
- 8K/4K/2K Bytes EEPROM
Endurance: 20’000 Write/Erase Cycles @ 125°C (100’000 Cycles @ 25°C)
- 32K/16K/8K Bytes Internal SRAM
JTAG (IEEE std. 1149.1 compliant) Interface
- Boundary-scan Capabilities According to the JTAG Standard
- Extensive On-chip Debug Support
- Programming of Flash EEPROM, Fuses and Lock Bits through the JTAG interface
Peripheral Features
- Multiple Timer/Counter & PWM channels
- Real Time Counter with Separate Oscillator
- 10-bit, 330 ks/s A/D Converter; Analog Comparator; On-chip Temperature Sensor
- Master/Slave SPI Serial Interface
- Two Programmable Serial USART
- Byte Oriented 2-wire Serial Interface
Advanced Interrupt Handler and Power Save Modes
Watchdog Timer with Separate On-Chip Oscillator
Power-on Reset and Low Current Brown-Out Detector
Fully integrated Low Power Transceiver for 2.4 GHz ISM Band
- High Power Amplifier support by TX spectrum side lobe suppression
- Supported Data Rates: 250 kb/s and 500 kb/s, 1 Mb/s, 2 Mb/s
- -100 dBm RX Sensitivity; TX Output Power up to 3.5 dBm
- Hardware Assisted MAC (Auto-Acknowledge, Auto-Retry)
- 32 Bit IEEE 802.15.4 Symbol Counter
- SFD-Detection, Spreading; De-Spreading; Framing ; CRC-16 Computation
- Antenna Diversity and TX/RX control / TX/RX 128 Byte Frame Buffer
PLL synthesizer with 5 MHz and 500 kHz channel spacing for 2.4 GHz ISM Band
Hardware Security (AES, True Random Generator)
Integrated Crystal Oscillators (32.768 kHz & 16 MHz, external crystal needed)
I/O and Package
- 33 Programmable I/O Lines
- 48-pad QFN (RoHS/Fully Green)
Temperature Range: -40°C to 125°C Industrial
Ultra Low Power consumption (1.8 to 3.6V) for AVR & Rx/Tx: 10.1mA/18.6 mA
- CPU Active Mode (16MHz): 4.1 mA
- 2.4GHz Transceiver: RX_ON 6.0 mA / TX 14.5 mA (maximum TX output power)
- Deep Sleep Mode: <700nA @ 25°C
Speed Grade: 0 – 16 MHz @ 1.8 – 3.6V range with integrated voltage regulators
8-bit
Microcontroller
with Low Power
2.4GHz
Transceiver for
ZigBee and
IEEE 802.15.4
ATmega2564RFR2
ATmega1284RFR2
ATmega644RFR2
Applications
ZigBee® / IEEE 802.15.4-2011/2006/2003– Full and Reduced Function Device
General Purpose 2.4GHz ISM Band Transceiver with Microcontroller
RF4CE, SP100, WirelessHART, ISM Applications and IPv6 / 6LoWPAN
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1 Pin Configurations
Figure 1-1. Pinout ATmega2564/1284/644RFR2
48 47 46 45 44 43 42 41 40 39 38 37
PF3/4:ADC3/4:TCK:DIG4 1
36 PE2:XCK0:AIN0
PF5:ADC5:TMS 2
35 PE1:TXD0
PF6:ADC6:TDO 3
34 PE0:RXD0:PCINT8
PF7:ADC7:TDI 4
ATmega2564/1284/644RFR2
33 PB7:OC0A:OC1C:PCINT7
AVSS_RFP 5
32 PB6:OC1B:PCINT6
RFP 6
QFN 48
31 PB5:OC1A:PCINT5
RFN 7
30 PB4:OC2A:PCINT4
AVSS_RFN 8
7x7 mm
29 PB3:MISO:PDO:PCINT3
TST 9
28 PB2:MOSI:PDI:PCINT2
RSTN 10
27 PB1:SCK:PCINT1
PG1:DIG1 11
26 PB0:SSN:PCINT0
PG3:TOSC2 12
25 CLKI
13 14 15 16 17 18 19 20 21 22 23 24
Note:
The large center pad underneath the QFN/MLF package is made of metal and internally connected
to AVSS. It should be soldered or glued to the board to ensure good mechanical stability. If the
center pad is left unconnected, the package might loosen from the board. It is not recommended to
use the exposed paddle as a replacement of the regular AVSS pins.
2 Disclaimer
Typical values contained in this datasheet are based on simulation and characterization
results of other AVR microcontrollers and radio transceivers manufactured in a similar
process technology. Minimum and Maximum values will be available after the device is
characterized.
2 ATmega2564/1284/644RFR2
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ATmega2564/1284/644RFR2
3 Overview
3.1 Block Diagram
The ATmega2564/1284/644RFR2 is a low-power CMOS 8-bit microcontroller based on
the AVR enhanced RISC architecture combined with a high data rate transceiver for the
2.4 GHz ISM band.
By executing powerful instructions in a single clock cycle, the device achieves
throughputs approaching 1 MIPS per MHz allowing the system designer to optimize
power consumption versus processing speed.
The radio transceiver provides high data rates from 250 kb/s up to 2 Mb/s, frame
handling, outstanding receiver sensitivity and high transmit output power enabling a
very robust wireless communication.
Figure 3-1 Block Diagram
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The AVR core combines a rich instruction set with 32 general purpose working
registers. All 32 registers are directly connected to the Arithmetic Logic Unit (ALU). Two
independent registers can be accessed with one single instruction executed in one
clock cycle. The resulting architecture is very code efficient while achieving throughputs
up to ten times faster than conventional CISC microcontrollers. The system includes
internal voltage regulation and an advanced power management. Distinguished by the
small leakage current it allows an extended operation time from battery.
The radio transceiver is a fully integrated ZigBee solution using a minimum number of
external components. It combines excellent RF performance with low cost, small size
and low current consumption. The radio transceiver includes a crystal stabilized
fractional-N synthesizer, transmitter and receiver, and full Direct Sequence Spread
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Spectrum Signal (DSSS) processing with spreading and despreading. The device is
fully compatible with IEEE802.15.4-2011/2006/2003 and ZigBee standards.
The ATmega2564/1284/644RFR2 provides the following features: 256K/128K/64K
Bytes of In-System Programmable (ISP) Flash with read-while-write capabilities,
8K/4K/2K Bytes EEPROM, 32K/16K/8K Bytes SRAM, up to 35 general purpose I/O
lines, 32 general purpose working registers, Real Time Counter (RTC), 6 flexible
Timer/Counters with compare modes and PWM, a 32 bit Timer/Counter, 2 USART, a
byte oriented 2-wire Serial Interface, a 8 channel, 10 bit analog to digital converter
(ADC) with an optional differential input stage with programmable gain, programmable
Watchdog Timer with Internal Oscillator, a SPI serial port, IEEE std. 1149.1 compliant
JTAG test interface, also used for accessing the On-chip Debug system and
programming and 6 software selectable power saving modes.
The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI port, and
interrupt system to continue functioning. The Power-down mode saves the register
contents but freezes the Oscillator, disabling all other chip functions until the next
interrupt or hardware reset. In Power-save mode, the asynchronous timer continues to
run, allowing the user to maintain a timer base while the rest of the device is sleeping.
The ADC Noise Reduction mode stops the CPU and all I/O modules except
asynchronous timer and ADC, to minimize switching noise during ADC conversions. In
Standby mode, the RC oscillator is running while the rest of the device is sleeping. This
allows very fast start-up combined with low power consumption. In Extended Standby
mode, both the main RC oscillator and the asynchronous timer continue to run.
Typical supply current of the microcontroller with CPU clock set to 16MHz and the radio
transceiver for the most important states is shown in the Figure 3-2 below.
Figure 3-2 Radio transceiver and microcontroller (16MHz) supply current
20
1.8V
3.0V
3.6V
15
RPC disabled 16,6mA
18,6mA
10 RPC enabled 10.1mA
5
4,1mA
4,7mA
275000nnA
0
Deep Sleep
SLEEP
TRX_OFF
RX_ON
BUSY_TX
Radio transceiver and microcontroller (16MHz) supply current
The transmit output power is set to maximum. If the radio transceiver is in SLEEP mode
the current is dissipated by the AVR microcontroller only.
In Deep Sleep mode all major digital blocks with no data retention requirements are
disconnected from main supply providing a very small leakage current. Watchdog timer,
MAC symbol counter and 32.768kHz oscillator can be configured to continue to run.
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ATmega2564/1284/644RFR2
The device is manufactured using Atmel’s high-density nonvolatile memory technology.
The On-chip ISP Flash allows the program memory to be reprogrammed in-system
trough an SPI serial interface, by a conventional nonvolatile memory programmer, or by
on on-chip boot program running on the AVR core. The boot program can use any
interface to download the application program in the application Flash memory.
Software in the boot Flash section will continue to run while the application Flash
section is updated, providing true Read-While-Write operation. By combining an 8 bit
RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel
ATmega2564/1284/644RFR2 is a powerful microcontroller that provides a highly
flexible and cost effective solution to many embedded control applications.
The ATmega2564/1284/644RFR2 AVR is supported with a full suite of program and
system development tools including: C compiler, macro assemblers, program
debugger/simulators, in-circuit emulators, and evaluation kits.
3.2 Pin Descriptions
3.2.1 EVDD
3.2.2 DEVDD
3.2.3 AVDD
3.2.4 DVDD
3.2.5 DVSS
3.2.6 AVSS
3.2.7 Port B (PB7...PB0)
3.2.8 Port D (PD7...PD0)
3.2.9 Port E (PE7,PE5...PE0)
External analog supply voltage.
External digital supply voltage.
Regulated analog supply voltage (internally generated).
Regulated digital supply voltage (internally generated).
Digital ground.
Analog ground.
Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each
bit). The Port B output buffers have symmetrical drive characteristics with both high sink
and source capability. As inputs, Port B pins that are externally pulled low will source
current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset
condition becomes active, even if the clock is not running.
Port B also provides functions of various special features of the
ATmega2564/1284/644RFR2.
Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each
bit). The Port D output buffers have symmetrical drive characteristics with both high sink
and source capability. As inputs, Port D pins that are externally pulled low will source
current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset
condition becomes active, even if the clock is not running.
Port D also provides functions of various special features of the
ATmega2564/1284/644RFR2.
Internally Port E is an 8-bit bi-directional I/O port with internal pull-up resistors (selected
for each bit). The Port E output buffers have symmetrical drive characteristics with both
high sink and source capability. As inputs, Port E pins that are externally pulled low will
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source current if the pull-up resistors are activated. The Port E pins are tri-stated when
a reset condition becomes active, even if the clock is not running.
Due to the low pin count of the QFN48 package port E6 is not connected to a pin.
Port E also provides functions of various special features of the
ATmega2564/1284/644RFR2.
3.2.10 Port F (PF7..PF5,PF4/3,PF2...PF0)
Internally Port F is an 8-bit bi-directional I/O port with internal pull-up resistors (selected
for each bit). The Port F output buffers have symmetrical drive characteristics with both
high sink and source capability. As inputs, Port F pins that are externally pulled low will
source current if the pull-up resistors are activated. The Port F pins are tri-stated when
a reset condition becomes active, even if the clock is not running.
Due to the low pin count of the QFN48 package port F3 and F4 are connected to the
same pin. The I/O configuration should be done carefully in order to avoid excessive
power dissipation.
Port F also provides functions of various special features of the
ATmega2564/1284/644RFR2.
3.2.11 Port G (PG4,PG3,PG1)
Internally Port G is a 6-bit bi-directional I/O port with internal pull-up resistors (selected
for each bit). The Port G output buffers have symmetrical drive characteristics with both
high sink and source capability. However the driver strength of PG3 and PG4 is
reduced compared to the other port pins. The output voltage drop (VOH, VOL) is higher
while the leakage current is smaller. As inputs, Port G pins that are externally pulled low
will source current if the pull-up resistors are activated. The Port G pins are tri-stated
when a reset condition becomes active, even if the clock is not running.
Due to the low pin count of the QFN48 package port G0, G2 and G5 are not connected
to a pin.
Port G also provides functions of various special features of the
ATmega2564/1284/644RFR2.
3.2.12 AVSS_RFP
AVSS_RFP is a dedicated ground pin for the bi-directional, differential RF I/O port.
3.2.13 AVSS_RFN
AVSS_RFN is a dedicated ground pin for the bi-directional, differential RF I/O port.
3.2.14 RFP
RFP is the positive terminal for the bi-directional, differential RF I/O port.
3.2.15 RFN
RFN is the negative terminal for the bi-directional, differential RF I/O port.
3.2.16 RSTN
Reset input. A low level on this pin for longer than the minimum pulse length will
generate a reset, even if the clock is not running. Shorter pulses are not guaranteed to
generate a reset.
3.2.17 XTAL1
Input to the inverting 16MHz crystal oscillator amplifier. In general a crystal between
XTAL1 and XTAL2 provides the 16MHz reference clock of the radio transceiver.
3.2.18 XTAL2
Output of the inverting 16MHz crystal oscillator amplifier.
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ATmega2564/1284/644RFR2
3.2.19 TST
3.2.20 CLKI
Programming and test mode enable pin. If pin TST is not used pull it to low.
Input to the clock system. If selected, it provides the operating clock of the
microcontroller.
3.3 Unused Pins
Floating pins can cause power dissipation in the digital input stage. They should be
connected to an appropriate source. In normal operation modes the internal pull-up
resistors can be enabled (in Reset all GPIO are configured as input and the pull-up
resistors are still not enabled).
Bi-directional I/O pins shall not be connected to ground or power supply directly.
The digital input pins TST and CLKI must be connected. If unused pin TST can be
connected to AVSS while CLKI should be connected to DVSS.
Output pins are driven by the device and do not float. Power supply pins respective
ground supply pins are connected together internally.
XTAL1 and XTAL2 shall never be forced to supply voltage at the same time.
3.4 Compatibility and Feature Limitations of QFN-48 Package
3.4.1 AREF
The reference voltage output of the A/D converter is not connected to a pin in the
ATmega2564/1284/644RFR2.
3.4.2 Port E6
The port E6 is not connected to a pin in the ATmega2564/1284/644RFR2. The alternate
pin functions as clock input to timer 3 and external interrupt 6 are not available.
3.4.3 Port F3 and F4
3.4.4 Port G0
The port F3 and F4 are connected to the same pin in the ATmega2564/1284/644RFR2.
The output configuration should be done carefully in order to avoid excessive current
consumption.
The alternate pin function of port F4 is used by the JTAG interface. If the JTAG
interface is used the port F3 must be configured as input and the alternate pin function
output DIG4 (RX/TX indicator) must be disabled. Otherwise the JTAG interface will not
work. The SPIEN Fuse should be programmed in order to be able to erase a program
that accidentally drive port F3.
There are just 7 single-ended input channel to the ADC available.
The port G0 is not connected to a pin in the ATmega2564/1284/644RFR2. The
alternate pin function DIG3 (inverted RX/TX indicator) is not available. If the JTAG
interface is not used the DIG4 alternate pin function output of port F3 can still be used
as RX/TX indicator.
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3.4.5 Port G2
The port G2 is not connected to a pin in the ATmega2564/1284/644RFR2. The
alternate pin function AMR (asynchronous automated meter reading input to timer 2) is
not available.
3.4.6 Port G5
The port G5 is not connected to a pin in the ATmega2564/1284/644RFR2. The
alternate pin function OC0B (output compare channel of 8-Bit timer 0) is not available.
3.4.7 RSTON
The RSTON reset output signaling the internal reset state is not connected to a pin in
the ATmega2564/1284/644RFR2.
4 Resources
A comprehensive set of development tools and application notes, and datasheets are
available for download on http://www.atmel.com.
5 About Code Examples
This documentation contains simple code examples that briefly show how to use
various parts of the device. Be aware that not all C compiler vendors include bit
definitions in the header files and interrupt handling in C is compiler dependent. Please
confirm with the C compiler documentation for more details.
These code examples assume that the part specific header file is included before
compilation. For I/O registers located in extended I/O map, "IN", "OUT", "SBIS", "SBIC",
"CBI", and "SBI" instructions must be replaced with instructions that allow access to
extended I/O. Typically "LDS" and "STS" combined with "SBRS", "SBRC", "SBR", and
"CBR".
6 Data Retention and Endurance
6.1 Data Retention
The data retention of the non-volatile memories is
over 10 years at 125°C
over 100 years at 25°C
6.2 Endurance of the Code Memory (FLASH)
The endurance of the code memory (FLASH) is
125°C – 10,000 Write/Erase cycles
85°C – 25,000 Write/Erase cycles
6.3 Endurance of the Data Memory (EEPROM)
The endurance of the entire data memory (EEPROM) is
125°C – 20,000 Write/Erase cycles
85°C – 50,000 Write/Erase cycles
25°C – 100,000 Write/Erase cycles
8 ATmega2564/1284/644RFR2
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ATmega2564/1284/644RFR2
7 AVR CPU Core
7.1 Introduction
This section discusses the AVR core architecture in general. The main function of the
CPU core is to ensure correct program execution. The CPU must therefore be able to
access memories, perform calculation, control peripherals, and handle interrupts.
7.2 Architectural Overview
Figure 7-1.Block Diagram of the AVR Architecture
Data Bus 8-bit
Flash
Program
Memory
Instruction
Register
Instruction
Decoder
Control Lines
Program
Counter
Status
and Control
32 x 8
General
Purpose
Registers
ALU
Interrupt
Unit
SPI
Unit
Watchdog
Timer
Analog
Comparator
Data
SRAM
EEPROM
I/O Module1
I/O Module 2
I/O Module n
I/O Lines
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In order to maximize performance and parallelism, the AVR uses a Harvard
architecture – with separate memories and buses for program and data. Instructions in
the program memory are executed with a single level pipelining. While one instruction is
being executed, the next instruction is pre-fetched from the program memory. This
concept enables instructions to be executed in every clock cycle. The program memory
is In-System Reprogrammable Flash memory.
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The fast-access Register File contains 32 x 8-bit general purpose working registers with
a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU)
operation. In a typical ALU operation, two operands are output from the Register File,
the operation is executed, and the result is stored back in the Register File – in one
clock cycle.
Six of the 32 registers can be used as three 16-bit indirect address register pointers for
Data Space addressing – enabling efficient address calculations. One of these address
pointers can also be used as an address pointer for look up tables in Flash program
memory. These added function registers are the 16-bit X-, Y-, and Z-register, described
later in this section.
The ALU supports arithmetic and logic operations between registers or between a
constant and a register. Single register operations can also be executed in the ALU.
After an arithmetic operation, the Status Register is updated to reflect information about
the result of the operation.
Program flow is provided by conditional and unconditional jump and call instructions,
able to directly address the whole address space. Most AVR instructions have a single
16-bit word format. Every program memory address contains a 16- or 32-bit instruction.
Program Flash memory space is divided in two sections, the Boot Program section and
the Application Program section. Both sections have dedicated Lock bits for write and
read/write protection. The SPM instruction that writes into the Application Flash memory
section must reside in the Boot Program section.
During interrupts and subroutine calls, the return address Program Counter (PC) is
stored on the Stack. The Stack is effectively allocated in the general data SRAM, and
consequently the Stack size is only limited by the total SRAM size and the usage of the
SRAM. All user programs must initialize the SP in the Reset routine (before subroutines
or interrupts are executed). The Stack Pointer (SP) is read/write accessible in the I/O
space. The data SRAM can easily be accessed through the five different addressing
modes supported in the AVR architecture.
The memory spaces in the AVR architecture are all linear and regular memory maps.
A flexible interrupt module has its control registers in the I/O space with an additional
Global Interrupt Enable bit in the Status Register. All interrupts have a separate
Interrupt Vector in the Interrupt Vector table. The interrupts have priority in accordance
with their Interrupt Vector position. The lower the Interrupt Vector address, the higher
the priority.
The I/O memory space contains 64 addresses for CPU peripheral functions as Control
Registers, SPI, and other I/O functions. The I/O Memory can be accessed directly, or as
the Data Space locations following those of the Register File, 0x20 - 0x5F. In addition,
the ATmega2564/1284/644RFR2 has Extended I/O space from 0x60 - 0x1FF in SRAM
where only the ST/STS/STD and LD/LDS/LDD instructions can be used.
7.3 ALU – Arithmetic Logic Unit
The high-performance AVR ALU operates in direct connection with all the 32 general
purpose working registers. Within a single clock cycle, arithmetic operations between
general purpose registers or between a register and an immediate are executed. The
ALU operations are divided into three main categories – arithmetic, logical, and bit
functions. Some implementations of the architecture also provide a powerful multiplier
supporting both signed/unsigned multiplication and fractional format. See the
“Instruction Set” section for a detailed description.
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ATmega2564/1284/644RFR2
7.4 Status Register
The Status Register contains information about the result of the most recently executed
arithmetic instruction. This information can be used for altering program flow in order to
perform conditional operations. Note that the Status Register is updated after all ALU
operations, as specified in the Instruction Set Reference. This will in many cases
remove the need for using the dedicated compare instructions, resulting in faster and
more compact code. The Status Register is not automatically stored when entering an
interrupt routine and restored when returning from an interrupt. This must be handled by
software.
7.4.1 SREG – Status Register
Bit 7 6 5 4 3 2 1 0
$3F ($5F)
I
T H S V N Z C SREG
Read/Write RW RW RW RW RW RW RW RW
Initial Value
0
0
0
0
0
0
0
0
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Bit 7 – I - Global Interrupt Enable
The global interrupt enable bit must be set (one) for the interrupts to be enabled. The
individual interrupt enable control is then performed in separate control registers. If the
global interrupt enable bit is cleared (zero), none of the interrupts are enabled
independent of the individual interrupt enable settings. The I-bit is cleared by hardware
after an interrupt has occurred, and is set by the RETI instruction to enable subsequent
interrupts.
Bit 6 – T - Bit Copy Storage
The bit copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T bit as source
and destination for the operated bit. A bit from a register in the register file can be
copied into T by the BST instruction, and a bit in T can be copied into a bit in a register
in the register file by the BLD instruction.
Bit 5 – H - Half Carry Flag
The half carry flag H indicates a half carry in some arithmetic operations. See the
Instruction Set Description for detailed information.
Bit 4 – S - Sign Bit
The S-bit is always an exclusive or between the negative flag N and the two's
complement overflow flag V. See the Instruction Set Description for detailed
information.
Bit 3 – V - Two's Complement Overflow Flag
The two's complement overflow flag V supports two's complement arithmetics. See the
Instruction Set Description for detailed information.
Bit 2 – N - Negative Flag
The negative flag N indicates a negative result after the different arithmetic and logic
operations. See the Instruction Set Description for detailed information.
Bit 1 – Z - Zero Flag
The zero flag Z indicates a zero result after the different arithmetic and logic operations.
See the Instruction Set Description for detailed information.
Bit 0 – C - Carry Flag
The carry flag C indicates a carry in an arithmetic or logic operation. See the Instruction
Set Description for detailed information. Note that the status register is not automatically
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stored when entering an interrupt routine and restored when returning from an interrupt
routine. This must be handled by software.
7.5 General Purpose Register File
The Register File is optimized for the AVR Enhanced RISC instruction set. In order to
achieve the required performance and flexibility, the following input/output schemes are
supported by the Register File:
One 8-bit output operand and one 8-bit result input
Two 8-bit output operands and one 8-bit result input
Two 8-bit output operands and one 16-bit result input
One 16-bit output operand and one 16-bit result input
Figure 7-1 below shows the structure of the 32 general purpose working registers in the
CPU.
Figure 7-1. AVR CPU General Purpose Working Registers
Most of the instructions operating on the Register File have direct access to all
registers, and most of them are single cycle instructions.
As shown in Figure 7-1 above each register is also assigned a data memory address,
mapping them directly into the first 32 locations of the user Data Space. Although not
being physically implemented as SRAM locations, this memory organization provides
great flexibility in access of the registers, as the X-, Y- and Z-pointer registers can be
set to index any register in the file.
7.5.1 The X-register, Y-register, and Z-register
The registers R26...R31 have some added functions to their general purpose usage.
These registers are 16-bit address pointers for indirect addressing of the data space.
The three indirect address registers X, Y, and Z are defined as described in Figure 7-2
on page 13.
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ATmega2564/1284/644RFR2
Figure 7-2. The X-, Y-, Z-registers
7.6 Stack Pointer
In the different addressing modes these address registers have functions as fixed
displacement, automatic increment, and automatic decrement (see the instruction set
reference for details).
The Stack is mainly used for storing temporary data, for storing local variables and for
storing return addresses after interrupts and subroutine calls. The Stack Pointer
Register always points to the top of the Stack. Note that the Stack is implemented as
growing from higher memory locations to lower memory locations. This implies that a
Stack PUSH command decreases the Stack Pointer.
The Stack Pointer points to the data SRAM Stack area where the Subroutine and
Interrupt Stacks are located. This Stack space in the data SRAM must be defined by
the program before any subroutine calls are executed or interrupts are enabled. The
Stack Pointer must be set to point above 0x0200. The initial value of the stack pointer is
the last address of the internal SRAM.
The Stack Pointer is decremented by one when data is pushed onto the Stack with the
PUSH instruction, and it is decremented by two when the return address is pushed onto
the Stack with subroutine call or interrupt. The Stack Pointer is incremented by one
when data is popped from the Stack with the POP instruction, and it is incremented by
two when data is popped from the Stack with return from subroutine RET or return from
interrupt RETI.
When the FLASH memory exceeds 128Kbyte one additional cycle is required. In this
case the Stack Pointer is decremented by three when the return address is pushed onto
the Stack with subroutine call or interrupt and is incremented by three when data is
popped from the Stack with return from subroutine RET or return from interrupt RETI.
Note:
1. If the Stack Pointer is zero and then decremented the new Stack Pointer value will
be different within the device family: 0xffff (256K Byte FLASH memory),
0x7fff (128 K Byte FLASH memory) and 0x03fff (64 K Byte FLASH memory),
respectively. Useful upper values of the Stack Pointer are defined by the SRAM
size.
7.6.1 SPH – Stack Pointer High
Bit
$3E ($5E)
Read/Write
Initial Value
7
SP15
RW
0
6
SP14
RW
0
5
SP13
RW
1
4
SP12
RW
0
3
SP11
RW
0
2
SP10
RW
0
1
SP9
RW
0
0
SP8
RW
1
SPH
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The AVR Stack Pointer is implemented as two 8-bit registers SPL and SPH in the I/O
space. The number of bits actually used is implementation dependent. Note that the
data space in some implementations of the AVR architecture is so small that only SPL
is needed. In this case, the SPH Register will not be present.
Bit 7:0 – SP15:8 - Stack Pointer High Byte
7.6.2 SPL – Stack Pointer Low
Bit 7 6 5 4 3 2 1 0
$3D ($5D) SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0
Read/Write RW RW RW RW RW RW RW RW
Initial Value
1
1
1
1
1
1
1
1
SPL
The AVR Stack Pointer is implemented as two 8-bit registers SPL and SPH in the I/O
space. The number of bits actually used is implementation dependent. Note that the
data space in some implementations of the AVR architecture is so small that only SPL
is needed. In this case, the SPH Register will not be present.
Bit 7:0 – SP7:0 - Stack Pointer Low Byte
7.6.3 RAMPZ – Extended Z-pointer Register for ELPM/SPM
Bit 7 6 5
$3B ($5B)
Read/Write
Initial Value
Res5
R
0
Res4
R
0
Res3
R
0
4
Res2
R
0
3
Res1
R
0
2
Res0
R
0
10
RAMPZ1 RAMPZ0
RW RW
00
RAMPZ
For ELPM/SPM instructions, the Z-pointer is a concatenation of RAMPZ, ZH, and ZL.
Note that LPM is not affected by the RAMPZ setting.
Bit 7:2 – Res5:0 - Reserved
For compatibility with future devices, be sure to write these bits to zero.
Bit 1:0 – RAMPZ1:0 - Extended Z-Pointer Value
Represent the MSB's of the Z-Pointer.
Table 7-2 RAMPZ Register Bits
Register Bits
RAMPZ1:0
Value
0
Description
Default value of Z-pointer MSB's.
For ELPM/SPM instructions, the Z-pointer is a concatenation of RAMPZ, ZH, and ZL,
as shown in Figure 7-3 below. Note that LPM is not affected by the RAMPZ setting.
Figure 7-3. The Z-pointer used by ELPM and SPM
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The actual number of bits is implementation dependent. Unused bits in an
implementation will always read as zero. For compatibility with future devices, be sure
to write these bits to zero.
7.6.4 EIND – Extended Indirect Register
Bit 7 6 5 4 3 2 1 0
$3C ($5C)
Read/Write
Initial Value
EIND0
RW
0
EIND
Bit 0 – EIND0 - Bit 0
For EICALL/EIJMP instructions.
7.7 Instruction Execution Timing
Figure 7-4. The Parallel Instruction Fetches and Instruction Executions
T1 T2 T3
clkCPU
1st Instruction Fetch
1st Instruction Execute
2nd Instruction Fetch
2nd Instruction Execute
3rd Instruction Fetch
3rd Instruction Execute
4th Instruction Fetch
T4
Figure 7-5 below shows the internal timing concept for the Register File. In a single
clock cycle an ALU operation using two register operands is executed, and the result is
stored back to the destination register.
Figure 7-5. Single Cycle ALU operation
T1
T2
T3
T4
clkCPU
Total Execution Time
Register Operands Fetch
ALU Operation Execute
Result Write Back
7.8 Reset and Interrupt Handling
The AVR provides several different interrupt sources. These interrupts and the separate
Reset Vector each have a separate program vector in the program memory space. All
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interrupts are assigned individual enable bits which must be written logic one together
with the Global Interrupt Enable bit in the Status Register in order to enable the
interrupt. Depending on the Program Counter value, interrupts may be automatically
disabled when Boot Lock bits BLB02 or BLB12 are programmed. This feature improves
software security. See the section "Memory Programming" on page 502 for details.
The lowest addresses in the program memory space are by default defined as the
Reset and Interrupt Vectors. The complete list of vectors is shown in "Interrupts" on
page 241. The list also determines the priority levels of the different interrupts. The
lower the address the higher is the priority level. RESET has the highest priority, and
next is INT0 – the External Interrupt Request 0. The Interrupt Vectors can be moved to
the start of the Boot Flash section by setting the IVSEL bit in the MCU Control Register
(MCUCR). Refer to "Interrupts" on page 241 for more information. The Reset Vector
can also be moved to the start of the Boot Flash section by programming the
BOOTRST Fuse, see "Memory Programming" on page 502.
When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts
are disabled. The user software can write logic one to the I-bit to enable nested
interrupts. All enabled interrupts can then interrupt the current interrupt routine. The I-bit
is automatically set when a Return from Interrupt instruction – RETI – is executed.
There are basically two types of interrupts. The first type is triggered by an event that
sets the Interrupt Flag. For these interrupts, the Program Counter is vectored to the
actual Interrupt Vector in order to execute the interrupt handling routine, and hardware
clears the corresponding Interrupt Flag. Interrupt Flags can also be cleared by writing a
logic one to the flag bit position(s) to be cleared. If an interrupt condition occurs while
the corresponding interrupt enable bit is cleared, the Interrupt Flag will be set and
remembered until the interrupt is enabled, or the flag is cleared by software. Similarly, if
one or more interrupt conditions occur while the Global Interrupt Enable bit is cleared,
the corresponding Interrupt Flag(s) will be set and remembered until the Global
Interrupt Enable bit is set, and will then be executed by order of priority.
The second type of interrupts will trigger as long as the interrupt condition is present.
These interrupts do not necessarily have Interrupt Flags. If the interrupt condition
disappears before the interrupt is enabled, the interrupt will not be triggered.
When the AVR exits from an interrupt, it will always return to the main program and
execute one more instruction before any pending interrupt is served.
Note that the Status Register is not automatically stored when entering an interrupt
routine, nor restored when returning from an interrupt routine. This must be handled by
software.
When using the CLI instruction to disable interrupts, the interrupts will be immediately
disabled. No interrupt will be executed after the CLI instruction, even if it occurs
simultaneously with the CLI instruction. The following example shows how this can be
used to avoid interrupts during the timed EEPROM write sequence.
Assembly Code Example
in r16, SREG ; store SREG value
cli ; disable interrupts during timed sequence
sbi EECR, EEMPE ; start EEPROM write
sbi EECR, EEPE
out SREG, r16 ; restore SREG value (I-bit)
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ATmega2564/1284/644RFR2
Assembly Code Example
C Code Example
char cSREG;
cSREG = SREG; /* store SREG value */
/* disable interrupts during timed sequence */
__disable_interrupt();
EECR |= (1<<EEMPE); /* start EEPROM write */
EECR |= (1<<EEPE);
SREG = cSREG; /* restore SREG value (I-bit) */
When using the SEI instruction to enable interrupts, the instruction following SEI will be
executed before any pending interrupts, as shown in this example.
Assembly Code Example
sei ; set Global Interrupt Enable
sleep; enter sleep, waiting for interrupt
; note: will enter sleep before any pending
; interrupt(s)
C Code Example
__enable_interrupt(); /* set Global Interrupt Enable */
__sleep(); /* enter sleep, waiting for interrupt */
/* note: will enter sleep before any pending interrupt(s) */
7.8.1 Interrupt Response Time
The interrupt execution response for all the enabled AVR interrupts is five clock cycles
minimum. After five clock cycles the program vector address for the actual interrupt
handling routine is executed. During these five clock cycle period, the Program Counter
is pushed onto the Stack. The vector is normally a jump to the interrupt routine, and this
jump takes three clock cycles. If an interrupt occurs during execution of a multi-cycle
instruction, this instruction is completed before the interrupt is served. If an interrupt
occurs when the MCU is in sleep mode, the interrupt execution response time is
increased by five clock cycles. This increase comes in addition to the start-up time from
the selected sleep mode.
A return from an interrupt handling routine takes five clock cycles. During these five
clock cycles, the Program Counter (three bytes) is popped back from the Stack, the
Stack Pointer is incremented by three, and the I-bit in SREG is set.
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8 AVR Memories
This section describes the different memories in the ATmega2564/1284/644RFR2. The
AVR architecture has two main memory spaces, the Data Memory and the Program
Memory space. In addition, the ATmega2564/1284/644RFR2 features an EEPROM
Memory for data storage. All three memory spaces are linear and regular.
8.1 In-System Reprogrammable Flash Program Memory
The ATmega2564/1284/644RFR2 contains FLASH_SIZE Bytes On-chip In-System
Reprogrammable Flash memory for program storage, see Figure 8-6 below. Since all
AVR instructions are 16 or 32 bits wide, the Flash is 16 bit wide. For software security,
the Flash Program memory space is divided into two sections, Boot Program section
and Application Program section.
The Flash memory has an endurance of at least 10'000 write/erase cycles. The
ATmega2564/1284/644RFR2 Program Counter (PC) is 16 bits wide, thus addressing
the required program memory locations. The operation of Boot Program section and
associated Boot Lock bits for software protection are described in detail in "Boot Loader
Support – Read-While-Write Self-Programming" on page 485. "Memory Programming"
on page 502 contains a detailed description on Flash data serial downloading using the
SPI pins or the JTAG interface.
Constant tables can be allocated within the entire program memory address space (see
the LPM – Load Program Memory instruction description and ELPM – Extended Load
Program Memory instruction description).
Timing diagrams for instruction fetch and execution are presented in "Instruction
Execution Timing" on page 15.
Figure 8-6. Program Flash Memory Map
Program Memory
Application Flash Section
$0000
Boot Flash Section
The application section of the Flash memory contains 3 user signature pages. These
pages can be used to store data that should never be modified by an application
program e.g. ID numbers, calibration data etc. For details see section "User Signature
Data" on page 505.
8.2 SRAM Data Memory
Figure 8-7 on page 19 shows how the ATmega2564/1284/644RFR2 SRAM Memory is
organized. The ATmega2564/1284/644RFR2 is a complex microcontroller with more
peripheral units than can be supported within the 64 location reserved in the Opcode for
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ATmega2564/1284/644RFR2
the IN and OUT instructions. For the Extended I/O space from $060 – $1FF in SRAM,
only the ST/STS/STD and LD/LDS/LDD instructions can be used.
The first Data Memory locations address both the Register File, the I/O Memory,
Extended I/O Memory, and the internal data SRAM. The first 32 locations address the
Register file, the next 64 location the standard I/O Memory, then 416 locations of
Extended I/O memory and the following locations address the internal data SRAM.
The five different addressing modes for the data memory cover: Direct, Indirect with
Displacement, Indirect, Indirect with Pre-decrement, and Indirect with Post-increment.
In the Register file, registers R26 to R31 feature the indirect addressing pointer
registers.
The direct addressing reaches the entire data space.
The Indirect with Displacement mode reaches 63 address locations from the base
address given by the Y- or Z-register.
When using register indirect addressing modes with automatic pre-decrement and post-
increment, the address registers X, Y, and Z are decremented or incremented.
The 32 general purpose working registers, 64 I/O registers, and the internal data SRAM
(SRAM_SIZE Bytes) in the ATmega2564/1284/644RFR2 are all accessible through all
these addressing modes. The Register File is described in "General Purpose Register
File" on page 12.
Figure 8-7. Data Memory Map
Data Memory
32 Registers
64 I/O Registers
416 Ext I/O Reg.
Internal SRAM
(32K/16K/8K x 8)
$0000 - $001F
$0020 - $005F
$0060 - $01FF
$0200
$21FF
$41FF
$81FF
$FFFF
8.2.1 Data Memory Access Times
This section describes the general access timing concepts for internal memory access.
Access to the internal data SRAM is performed in two clkCPU cycles as described in
Figure 8-8 on page 20.
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Figure 8-8. On-Chip Data SRAM Access Cycles
T1 T2
clk
CPU
Address
Data
WR
Data
RD
Compute Address
Address valid
T3
Memory Access Instruction
Next Instruction
8.3 EEPROM Data Memory
The ATmega2564/1284/644RFR2 contains EEPROM_SIZE Bytes of data EEPROM
memory. It is organized as a separate data space. Read access is byte-wise. The
access between the EEPROM and the CPU is described in the following, specifying the
EEPROM Address Registers, the EEPROM Data Register, and the EEPROM Control
Register.
For a detailed description of SPI, JTAG and Parallel data downloading to the EEPROM,
see "Serial Downloading" on page 519, "Programming via the JTAG Interface" on page
523, and "Programming the EEPROM" on page 533 respectively.
8.3.1 EEPROM Read Write Access
The EEPROM Access Registers are accessible in the I/O space, see "EEPROM
Register Description" on page 26.
The write access time for the EEPROM is given in Table 8-3 below. A self-timing
function, however, lets the user software detect when the next byte can be written. If the
user code contains instructions that write the EEPROM, some precautions must be
taken. In heavily filtered power supplies, DVDD is likely to rise or fall slowly on power-
up/down. This causes the device for some period of time to run at a voltage lower than
specified as minimum for the clock frequency used. See "Preventing EEPROM
Corruption" on page 26 for details on how to avoid problems in these situations.
In order to prevent unintentional EEPROM writes, a specific write procedure must be
followed. See the description of the EEPROM Control Register for details on this,
"EEPROM Register Description" on page 26.
When the EEPROM is read, the CPU is halted for four clock cycles before the next
instruction is executed. When the EEPROM is written, the CPU is halted for two clock
cycles before the next instruction is executed.
The calibrated oscillator is used to time the EEPROM accesses. The following table
lists the typical programming time for EEPROM access from the CPU.
Table 8-3. EEPROM Programming Time
Symbol
Typical Programming time
EEPROM write (from CPU)
EEPROM erase (from CPU)
4.5 ms
8.5 ms
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The subsequent code examples show assembly and C functions for programming the
EEPROM with separate and combined (atomic) erase/write operations respectively.
The examples assume that interrupts are controlled (e.g. by disabling interrupts
globally) so that no interrupts will occur during execution of these functions. The
examples also assume that no Flash Boot Loader is present in the software. If such
code is present, the EEPROM write function must also wait for any ongoing SPM
command to finish.
Assembly Code Example (Single Byte Programming)
EEPROM_write:
; Wait for completion of previous erase/write
sbic EECR,EEPE
rjmp EEPROM_write
; Set up address (r18:r17) in address register
out EEARH, r18
out EEARL, r17
; Write data (r16) to Data Register
out EEDR,r16
; Write is controlled with r20 and r21
ldi r20, (1<<EEMPE) + (2<<EEPM0)
ldi r21, (1<<EEMPE) + (1<<EEPE) + (2<<EEPM0)
; Start eeprom write
out EECR, r20
out EECR, r21
ret
EEPROM_erase:
; Wait for completion of previous erase/write
sbic EECR,EEPE
rjmp EEPROM_erase
; Set up address (r18:r17) in address register
out EEARH, r18
out EEARL, r17
; Set EEDR to 0xff
ser r16
out EEDR,r16
; Erase is controlled with r20 and r21
ldi r20, (1<<EEMPE) + (1<<EEPM0)
ldi r21, (1<<EEMPE) + (1<<EEPE) + (1<<EEPM0)
; Start eeprom erase
out EECR, r20
out EECR, r21
ret
; main program
ldi r17, addr_low
ldi r18, addr_high
call EEPROM_erase
ldi r16, ee_data
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call EEPROM_write
C Code Example (Single Byte Programming)
void EEPROM_write(unsigned int uiAddress, unsigned char ucData)
{
/* Wait for completion of previous erase/write */
while(EECR & (1<<EEPE))
;
/* Set up address */
EEAR = uiAddress;
EEDR = 255;
/* Write logical one to EEMPE and enable erase only*/
EECR = (1<<EEMPE) + (1<<EEPM0);
/* Start eeprom erase by setting EEPE */
EECR |= (1<<EEPE);
/* Wait for completion of erase */
while(EECR & (1<<EEPE))
;
/* Set up Data Registers */
EEDR = ucData;
/* Write logical one to EEMPE and enable write only */
EECR = (1<<EEMPE) + (2<<EEPM0);
/* Start eeprom write by setting EEPE */
EECR |= (1<<EEPE);
}
Although the code for separate erase/write operations is more complex it is
recommended over the atomic operation. The erase operation can be omitted if the
target EEPROM byte already contains the value 255 (e.g. after a chip erase without the
EESAVE fuse set).
Assembly Code Example (Atomic Operation)
EEPROM_atomic_write:
; Wait for completion of previous write
sbic EECR,EEPE
rjmp EEPROM_atomic_write
; Set up address (r18:r17) in address register
out EEARH, r18
out EEARL, r17
; Write data (r16) to Data Register
out EEDR,r16
; Write logical one to EEMPE
sbi EECR,EEMPE
; Start eeprom write by setting EEPE
sbi EECR,EEPE
ret
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C Code Example (Atomic Operation)
void EEPROM_atomic_write(unsigned int uiAddress, unsigned char ucData)
{
/* Wait for completion of previous write */
while(EECR & (1<<EEPE))
;
/* Set up address and Data Registers */
EEAR = uiAddress;
EEDR = ucData;
/* Write logical one to EEMPE */
EECR |= (1<<EEMPE);
/* Start eeprom write by setting EEPE */
EECR |= (1<<EEPE);
}
The next code examples show assembly and C functions for reading the EEPROM. The
examples assume that interrupts are controlled so that no interrupts will occur during
execution of these functions.
Assembly Code Example (EEPROM Read)
EEPROM_read:
; Wait for completion of previous write
sbic EECR,EEPE
rjmp EEPROM_read
; Set up address (r18:r17) in address register
out EEARH, r18
out EEARL, r17
; Start eeprom read by writing EERE
sbi EECR,EERE
; Read data from Data Register
in r16,EEDR
ret
C Code Example (EEPROM Read)
unsigned char EEPROM_read(unsigned int uiAddress)
{
/* Wait for completion of previous write */
while(EECR & (1<<EEPE))
;
/* Set up address register */
EEAR = uiAddress;
/* Start eeprom read by writing EERE */
EECR |= (1<<EERE);
/* Return data from Data Register */
return EEDR;
}
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The programming time can be reduced if an entire 8 byte EEPROM page is
programmed instead of single bytes. In this case the data has to be loaded into the
page buffer first. The page buffer will auto-erase after a write or erase operation. It is
also erased after a system reset. Note that it is not possible to write more than one time
to each address without erasing the page buffer. The EEPROM page programming is
shown in following example code.
Assembly Code Example (Page Mode Programming)
EEPROM_pageerase:
sbic EECR,EEPE
; wait for completion of previous
rjmp EEPROM_pageerase ; EEPROM erase/write
; Page buffer loading is controlled with r20 and r21
ldi r20, (3<<EEPM0) + (1<<EEMPE)
ldi r21, (3<<EEPM0) + (1<<EEMPE) + (1<<EEPE)
ldi r16, 7
; EEPROM page has 8 bytes, loop 7 bytes
ser r16
out EEDR,r16
; set EEDR to 0xff
er_page_load:
out EEARL, r17
; set up address in page buffer
out EECR, r20
out EECR, r21
er_load_wait:
sbic EECR, EEWE
; wait for load complete
rjmp er_load_wait
dec r17
; decrement address counter
dec r16
; decrement loop counter
brne er_page_load
; complete loading of 7 bytes
; Erase is controlled with r20 and r21, load 8th byte
ldi r20, (1<<EEMPE) + (1<<EEPM0)
ldi r21, (1<<EEMPE) + (1<<EEPE) + (1<<EEPM0)
out EEARL, r17
; set up address, low byte (8th byte)
out EEARH, r18
; set up address, high byte
out EECR, r20
; start EEPROM page erase
out EECR, r21
ret
; main program
ldi r17, addr_low
ldi r18, addr_high
call EEPROM_pageerase
C Code Example (Page Mode Programming)(1,2)
void EEPROM_pagewrite(uint16_t uiAddress, uint8_t *ucData)
{
uint8_t byte_cnt = 0;
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while(EECR & (1<<EEPE)); // wait finish of previous erase/write
EEAR = uiAddress;
// set up address
EEDR = 255;
// data for erase
do {
EECR = (1<<EEMPE) + (3<<EEPM0); // enable buffer load only
EECR |= (1<<EEPE);
// start EEPROM loading
while(EECR & (1<<EEPE));
// wait for loading complete
EEARL++;
// next address
} while( ++byte_cnt<7 );
EECR = (1<<EEMPE) + (1<<EEPM0);
EECR |= (1<<EEPE);
while(EECR & (1<<EEPE));
// load last byte, erase only
// start EEPROM erase
// wait for erase complete
EEAR = uiAddress;
// set up address
byte_cnt = 0;
do {
EEDR = ucData[byte_cnt];
// load data from SRAM
EECR = (1<<EEMPE) + (3<<EEPM0); // enable buffer load only
EECR |= (1<<EEPE);
// start EEPROM loading
while(EECR & (1<<EEPE));
// wait for loading complete
EEARL++;
// next address
} while( ++byte_cnt<7 );
EEDR = ucData[byte_cnt];
// set up last data byte
EECR = (1<<EEMPE) + (2<<EEPM0); // load last byte, write only
EECR |= (1<<EEPE);
// start EEPROM write
}
int main(void)
{
uint8_t buffer[8];
// load buffer
EEPROM_pagewrite(0x000, &buffer[0] );
}
// write EEPROM page 0
Notes:
1. The example code assumes that the part specific header file is included.
2. See section "About Code Examples" on page 8.
The EEPROM page buffer can be loaded in arbitrary order. The data in the page buffer
can also be overwritten. Loading the last byte and executing the EEPROM
programming is one command. This programming command can be an erase, a write
or a combined atomic erase/write operation just like for single byte programming mode.
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8.3.2 Preventing EEPROM Corruption
During periods of low DEVDD, the EEPROM data can be corrupted because the supply
voltage is too low for the CPU and the EEPROM to operate properly. These issues are
the same as for board level systems using EEPROM, and the same design solutions
should be applied.
An EEPROM data corruption can be caused by two situations when the voltage is too
low. First, a regular write sequence to the EEPROM requires a minimum voltage to
operate correctly. Secondly, the CPU itself can execute instructions incorrectly, if the
supply voltage is too low.
EEPROM data corruption can easily be avoided by following this design
recommendation:
Keep the AVR RESET active (low) during periods of insufficient power supply voltage.
This can be done by enabling the internal Brown-out Detector (BOD). If the detection
level of the internal BOD does not match the needed detection level, an external low
DEVDD reset protection circuit can be used. If a reset occurs while a write operation is
in progress, the write operation will be completed provided that the power supply
voltage is sufficient.
8.4 EEPROM Register Description
8.4.1 EEARH – EEPROM Address Register High Byte
Bit 7 6
$22 ($42)
Read/Write
Initial Value
Res3
R
0
Res2
R
0
5
Res1
R
0
4
Res0
R
0
321
EEAR11 EEAR10
RW RW
XX
EEAR9
RW
X
0
EEAR8
RW
X
EEARH
The EEPROM Address Registers EEARH and EEARL specify the EEPROM address in
the 4K bytes EEPROM space. The EEPROM data bytes are addressed linearly
between 0 and 4096. The initial value of EEAR is undefined. A proper value must be
written before the EEPROM may be accessed.
Bit 7:4 – Res3:0 - Reserved
Bit 3:0 – EEAR11:8 - EEPROM Address
8.4.2 EEARL – EEPROM Address Register Low Byte
Bit
$21 ($41)
Read/Write
Initial Value
7
EEAR7
RW
X
6
EEAR6
RW
X
5
EEAR5
RW
X
4
EEAR4
RW
X
3
EEAR3
RW
X
2
EEAR2
RW
X
1
EEAR1
RW
X
0
EEAR0
RW
X
EEARL
The EEPROM Address Registers EEARH and EEARL specify the EEPROM address in
the 4K bytes EEPROM space. The EEPROM data bytes are addressed linearly
between 0 and 4096. The initial value of EEAR is undefined. A proper value must be
written before the EEPROM may be accessed.
Bit 7:0 – EEAR7:0 - EEPROM Address
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8.4.3 EEDR – EEPROM Data Register
Bit 7 6 5 4 3 2 1 0
$20 ($40)
EEDR7:0
Read/Write RW RW RW RW RW RW RW RW
Initial Value 0 0 0 0 0 0 0 0
EEDR
For the EEPROM write operation, the EEDR Register contains the data to be written to
the EEPROM in the address given by the EEAR Register. For the EEPROM read
operation, the EEDR contains the data read out from the EEPROM at the address given
by EEAR.
Bit 7:0 – EEDR7:0 - EEPROM Data
8.4.4 EECR – EEPROM Control Register
Bit
$1F ($3F)
Read/Write
Initial Value
7
Res1
R
0
6
Res0
R
0
5
EEPM1
RW
X
4
EEPM0
RW
X
3
EERIE
RW
0
2
EEMPE
RW
0
1
EEPE
RW
X
0
EERE
RW
0
EECR
Bit 7:6 – Res1:0 - Reserved
Bit 5:4 – EEPM1:0 - EEPROM Programming Mode
The EEPROM Programming mode bit setting defines if a page buffer load or a
programming action will be triggered when writing EEPE. It is possible to program data
in one atomic operation (erase the old value and program the new value) or to split the
Erase and Write operations in two different operations. While EEPE is set, any write to
EEPM1:0 will be ignored. During reset, the EEPM1:0 bits will be reset to 0 unless the
EEPROM is busy programming.
Table 8-4 EEPM Register Bits
Register Bits
Value
Description
EEPM1:0
0x00
0x01
0x02
0x03
Erase and Write in one operation (Atomic
Operation)
Erase only
Write only
Page buffer load
Bit 3 – EERIE - EEPROM Ready Interrupt Enable
Writing EERIE to one enables the EEPROM Ready Interrupt if the I bit in SREG is set.
Writing EERIE to zero disables the interrupt. The EEPROM Ready interrupt generates a
constant interrupt when EEPE is cleared.
Bit 2 – EEMPE - EEPROM Master Write Enable
The EEMPE bit determines whether setting EEPE to one causes the EEPROM to be
written or the page buffer to be loaded. When EEMPE is set, setting EEPE within four
clock cycles will either start programming the EEPROM or load data to the EEPROM
page buffer at the selected address If EEMPE is zero, setting EEPE will have no effect.
When EEMPE has been written to one by software, hardware clears the bit to zero after
four clock cycles. See the description of the EEPE bit for an EEPROM write procedure.
Bit 1 – EEPE - EEPROM Programming Enable
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The EEPROM Programming Enable Signal EEPE is the write strobe to the EEPROM. It
triggers either the programming or the page buffer loading. When address and data are
correctly set up, the EEPE bit must be written to one to write the value into the
EEPROM. The EEMPE bit must be written to one before a logical one is written to
EEPE, otherwise no EEPROM write or load takes place. The following procedure
should be adopted when writing or loading the EEPROM (the order of steps 3 and 4 is
not essential):
1. Wait until EEPE becomes zero.
2. Wait until SPMEN in SPMCSR becomes zero.
3. Write new EEPROM address to EEAR (optional).
4. Write new EEPROM data to EEDR (optional).
5. Write a logical one to the EEMPE bit while writing a zero to EEPE in EECR.
6. Within four clock cycles after setting EEMPE, write a logical one to EEPE.
The EEPROM can not be programmed and the page buffer not be loaded during a CPU
write to the Flash memory. The software must check that the Flash programming is
completed before initiating a new EEPROM write. Step 2 is only relevant if the software
contains a Boot Loader allowing the CPU to program the Flash. If the Flash is never
being updated by the CPU, step 2 can be omitted.
Caution: an interrupt between step 5 and step 6 will make the write cycle fail, since the
EEPROM Master Write Enable will time-out. If an interrupt routine accessing the
EEPROM is interrupting another EEPROM access, the EEAR or EEDR Register will be
modified, causing the interrupted EEPROM access to fail. It is recommended to have
the Global Interrupt Flag cleared during all steps to avoid these problems.
When the write access time has elapsed, the EEPE bit is cleared by hardware. The
user software can poll this bit and wait for a zero before writing the next byte. When
EEPE has been set, the CPU is halted for two cycles before the next instruction is
executed.
Bit 0 – EERE - EEPROM Read Enable
The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the
correct address is set up in the EEAR Register, the EERE bit must be written to a logic
one to trigger the EEPROM read. The EEPROM read access takes one instruction and
the requested data is available immediately. When the EEPROM is read, the CPU is
halted for four cycles before the next instruction is executed. The user should poll the
EEPE bit before starting the read operation. If a write operation is in progress, it is
neither possible to read the EEPROM nor to change the EEAR Register.
8.5 I/O Memory
The Input/Output (I/O) space definition of the ATmega2564/1284/644RFR2 is shown in
"Register Summary" on page 540.
All ATmega2564/1284/644RFR2 I/Os and peripherals are placed in the I/O space. All
I/O locations may be accessed by the LD/LDS/LDD and ST/STS/STD instructions,
transferring data between the 32 general purpose working registers and the I/O space.
I/O Registers within the address range 0x00 – 0x1F are directly bit-accessible using the
SBI and CBI instructions. In these registers, the value of single bits can be checked by
using the SBIS and SBIC instructions. Refer to the AVR instruction set for more details.
When using the I/O specific commands IN and OUT, the I/O addresses 0x00 – 0x3F
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ATmega2564/1284/644RFR2
must be used. When addressing I/O Registers as data space using LD and ST
instructions, 0x20 must be added to these addresses. The
ATmega2564/1284/644RFR2 is a complex microcontroller with more peripheral units
than can be supported within the 64 location reserved in Opcode for the IN and OUT
instructions. For the Extended I/O space from 0x60 – 0x1FF in SRAM, only the
ST/STS/STD and LD/LDS/LDD instructions can be used.
For compatibility with future devices, reserved bits may not be modified. Reserved
registers and I/O memory addresses should never be written.
Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike
most other AVRs, the CBI and SBI instructions will only operate on the specified bit,
and can therefore be used on registers containing such Status Flags. The CBI and SBI
instructions work with registers 0x00 to 0x1F only.
The control registers of I/O and peripherals are explained in later sections.
8.6 General Purpose I/O Registers
The ATmega2564/1284/644RFR2 contains three General Purpose I/O Registers.
These registers can be used for storing any information, and they are particularly useful
for storing global variables and Status Flags. General Purpose I/O Registers within the
address range 0x00 – 0x1F are directly bit-accessible using the SBI, CBI, SBIS, and
SBIC instructions.
8.6.1 GPIOR0 – General Purpose IO Register 0
Bit 7 6 5 4 3 2 1 0
$1E ($3E)
GPIOR07:00
Read/Write RW RW RW RW RW RW RW RW
Initial Value 0 0 0 0 0 0 0 0
GPIOR0
The three General Purpose I/O Registers can be used for storing any information.
Bit 7:0 – GPIOR07:00 - General Purpose I/O Register 0 Value
8.6.2 GPIOR1 – General Purpose IO Register 1
Bit 7 6 5 4 3 2 1 0
$2A ($4A)
GPIOR17:10
Read/Write RW RW RW RW RW RW RW RW
Initial Value 0 0 0 0 0 0 0 0
GPIOR1
The three General Purpose I/O Registers can be used for storing any information.
Bit 7:0 – GPIOR17:10 - General Purpose I/O Register 1 Value
8.6.3 GPIOR2 – General Purpose I/O Register 2
Bit 7 6 5 4 3 2 1 0
$2B ($4B)
GPIOR27:20
Read/Write RW RW RW RW RW RW RW RW
Initial Value 0 0 0 0 0 0 0 0
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The three General Purpose I/O Registers can be used for storing any information.
Bit 7:0 – GPIOR27:20 - General Purpose I/O Register 2 Value
8.7 Other Port Registers
The inherited control registers of missing ports located in the I/O space are kept in the
ATmega2564/1284/644RFR2. They can be used as general purpose I/O registers for
storing any information. Registers placed in the address range 0x00 – 0x1F are directly
bit-accessible using the SBI, CBI, SBIS and SBIC instructions.
8.7.1 PORTA – Port A Data Register
Bit 7 6 5 4 3 2 1 0
$02 ($22)
PORTA7:0
Read/Write RW RW RW RW RW RW RW RW
Initial Value 0 0 0 0 0 0 0 0
PORTA
The PORTA register can be used as a General Purpose I/O Register for storing any
information.
Bit 7:0 – PORTA7:0 - Port A Data Register Value
8.7.2 DDRA – Port A Data Direction Register
Bit 7
$01 ($21)
Read/Write
Initial Value
DDA7
RW
0
6
DDA6
RW
0
5
DDA5
RW
0
4
DDA4
RW
0
3
DDA3
RW
0
2
DDA2
RW
0
1
DDA1
RW
0
0
DDA0
RW
0
DDRA
The DDRA register can be used as a General Purpose I/O Register for storing any
information.
Bit 7:0 – DDA7:0 - Port A Data Direction Register Value
8.7.3 PINA – Port A Input Pins Address
Bit 7 6 5 4 3 2 1 0
$00 ($20)
PINA7:0
Read/Write RW RW RW RW RW RW RW RW
Initial Value 0 0 0 0 0 0 0 0
PINA
The PINA register is reserved for internal use and cannot be used as a General
Purpose I/O Register.
Bit 7:0 – PINA7:0 - Port A Input Pins
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