Q0170RA Datasheet PDF
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FSQ0170RNA, FSQ0270RNA
Green Mode Fairchild Power Switch (FPS™)
October 2011
Features
Internal Avalanche Rugged 700V SenseFET
Consumes only 0.8W at 230 VAC & 0.5W Load with
Burst-Mode Operation
Precision Fixed Operating Frequency, 100kHz
Internal Start-up Circuit and Built-in Soft-Start
Pulse-by-Pulse Current Limiting and Auto-Restart
Mode
Over-Voltage Protection (OVP), Overload Protection
(OLP), Internal Thermal Shutdown Function (TSD)
Under-Voltage Lockout (UVLO)
Low Operating Current (3mA)
Adjustable Peak Current Limit
Applications
Auxiliary Power Supply for PC and Server
SMPS for VCR, SVR, STB, DVD & DVCD Player,
Printer, Facsimile & Scanner
Adapter for Camcorder
Description
The FSQ0170RNA, and FSQ0270RNA, consists of an
integrated current mode Pulse Width Modulator (PWM)
and an avalanche-rugged 700V Sense FET. It is
specifically designed for high-performance off-line
Switch Mode Power Supplies (SMPS) with minimal
external components. The integrated PWM controller
features include: a fixed-frequency generating oscillator,
Under-Voltage Lockout (UVLO) protection, Leading
Edge Blanking (LEB), an optimized gate turn-on/ turn-off
driver, Thermal Shutdown (TSD) protection, and
temperature compensated precision current sources for
loop compensation and fault protection circuitry.
Compared to a discrete MOSFET and controller or RCC
switching converter solution, the FSQ0170RNA, and
FSQ0270RNA reduces total component count, design
size, and weight while increasing efficiency, productivity,
and system reliability. These devices provide a basic
platform that is well suited for the design of cost-effective
flyback converters, as in PC auxiliary power supplies.
Related Application Notes
AN-4134: Design Guidelines for Off-line Forward
Converters Using Fairchild Power Switch (FPS™)
AN-4137: Design Guidelines for Off-line Flyback
Converters Using Fairchild Power Switch (FPS™)
AN-4141: Troubleshooting and Design Tips for
Fairchild Power Switch (FPS™) Flyback Applications
AN-4147: Design Guidelines for RCD Snubber of
Flyback
AN-4148: Audible Noise Reduction Techniques for
FPS™ Applications
8-DIP
Ordering Information
Product Number
FSQ0170RNA
FSQ0270RNA
Package
8DIP
8DIP
Marking Code
Q0170RA
Q0270RA
BVDSS
700V
700V
fOSC
100kHz
100kHz
RDS(ON) (MAX.)
11
7.2
FPSTM is a trademark of Fairchild Semiconductor Corporation.
© 2006 Fairchild Semiconductor Corporation
FSQ0170RNA, FSQ0270RNA Rev. 1.0.5
www.fairchildsemi.com


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Application Diagram
AC
IN
Vstr Drain
IPK PWM
FB VCC GND
DC
OUT
FSQ0x70RNA Rev. 1.01
Figure 1. Typical Flyback Application
Output Power Table(1)
Product
230VAC 15%(2)
Adapter(3)
Open Frame(4)
85–265VAC
Adapter(3)
Open Frame(4)
FSQ0170RNA
14W
20W
9W
13W
FSQ0270RNA
17W
24W
11W
16W
Notes:
1. The maximum output power can be limited by junction temperature.
2. 230 VAC or 100/115 VAC with doubler.
3. Typical continuous power in a non-ventilated enclosed adapter with sufficient drain pattern as a heat sink, at 50C
ambient.
4. Maximum practical continuous power in an open-frame design with sufficient drain pattern as a heat sink, at 50C
ambient.
Internal Block Diagram
VCC
2
FB 3
IPK 4
VBURL/VBURH
VCC
VCC
IDELAY
IFB
8V/12V
Normal
2.5R
R
Burst
Vstr
5
ICH
VCC good
Vref
Internal
Bias
OSC
PWM
SQ
RQ
Gate
Driver
LEB
Drain
6,7,8
VSD
VCC
Vovp
TSD
VCC good
SQ
RQ
Figure 2. Internal Block Diagram
1 GND
Soft-Start
FSQ0x70RNA Rev. 1.00
© 2006 Fairchild Semiconductor Corporation
FSQ0170RNA, FSQ0270RNA Rev. 1.0.5
2
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Pin Configuration
GND
VCC
FB
IPK
8-DIP
D
D
D
Vstr
FSQ0x70RNA Rev. 1.00
Figure 3. Pin Configuration (Top View)
Pin Definitions
Pin #
Name
1 GND
2 VCC
3 FB
4 IPK
5 Vstr
6 Drain
7 Drain
8 Drain
Description
Ground. SenseFET source terminal on primary side and internal control
ground.
Power Supply. Positive supply voltage input. Although connected to an aux-
iliary transformer winding, current is supplied from pin 5 (Vstr) via an internal
switch during start-up, see Figure 2. It is not until VCC reaches the UVLO upper
threshold (12V) that the internal start-up switch opens and device power is
supplied via the auxiliary transformer winding.
Feedback. The feedback voltage pin is the non-inverting input to the PWM
comparator. It has a 0.9mA current source connected internally while a capac-
itor and opto-coupler are typically connected externally. A feedback voltage of
6V triggers overload protection (OLP). There is a time delay while charging ex-
ternal capacitor CFB from 3V to 6V using an internal 5µA current source. This
time delay prevents false triggering under transient conditions, but still allows
the protection mechanism to operate under true overload conditions.
Peak Current Limit. This pin adjusts the peak current limit of the SenseFET.
The 0.9mA feedback current source is diverted to the parallel combination of
an internal 2.8kresistor and any external resistor to GND on this pin. This
determines the peak current limit. If this pin is tied to VCC or left floating, the
typical peak current limit is 0.8A (FSQ0170RNA), 0.9A (FSQ0270RNA).
Start-up. This pin connects to the rectified AC line voltage source. At start-up,
the internal switch supplies internal bias and charges an external storage ca-
pacitor placed between the VCC pin and ground. Once the VCC reaches 12V,
the internal switch is opened.
SenseFET drain. High-voltage power SenseFET drain connection.
SenseFET drain. High-voltage power SenseFET drain connection.
SenseFET drain. High-voltage power SenseFET drain connection.
© 2006 Fairchild Semiconductor Corporation
FSQ0170RNA, FSQ0270RNA Rev. 1.0.5
3
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Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In
addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only
Symbol
Characteristic
Value
VDRAIN
VSTR
IDM
Drain Pin Voltage
Vstr Pin Voltage
Drain Current Pulsed(5)
FSQ0170RNA
FSQ0270RNA
700
700
4
8
EAS
Single Pulsed Avalanche Energy(6)
FSQ0170RNA
FSQ0270RNA
50
140
VCC
VFB
PD
TJ
TA
TSTG
Supply Voltage
Feedback Voltage Range
Total Power Dissipation
Operating Junction Temperature
Operating Ambient Temperature
Storage Temperature
20
-0.3 to VCC
1.5
Internally limited
-25 to +85
-55 to +150
Notes:
5. Non-repetitive rating: Pulse width is limited by maximum junction temperature.
6. L = 51mH, starting TJ = 25C.
Unit
V
V
A
mJ
V
V
W
C
C
C
Thermal Impedance
TA = 25C, unless otherwise specified. All items are tested with the standards JESD 51-2 and 51-10 (DIP).
Symbol
JA
JC
JT
Parameter
Junction-to-Ambient Thermal Resistance(7)
Junction-to-Case Thermal Resistance(8)
Junction-to-Top Thermal Resistance(9)
Value
80
20
35
Unit
C/W
C/W
C/W
Notes:
7. Free standing with no heatsink; without copper clad.
(Measurement Condition - Just before junction temperature TJ enters into OTP.)
8. Measured on the DRAIN pin close to plastic interface.
9. Measured on the PKG top surface.
© 2006 Fairchild Semiconductor Corporation
FSQ0170RNA, FSQ0270RNA Rev. 1.0.5
4
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Electrical Characteristics
TA = 25C unless otherwise specified.
Symbol
SenseFET Section(10)
Parameter
IDSS Zero-Gate-Voltage Drain Current
RDS(ON)
Drain-Source
On-State
Resistance(11)
FSQ0170RNA
FSQ0270RNA
CISS
Input Capacitance
FSQ0170RNA
FSQ0270RNA
COSS
Output Capacitance
FSQ0170RNA
FSQ0270RNA
CRSS
Reverse Transfer
Capacitance
FSQ0170RNA
FSQ0270RNA
td(on)
Turn-On Delay Time
FSQ0170RNA
FSQ0270RNA
tr Rise Time
FSQ0170RNA
FSQ0270RNA
td(off)
Turn-Off Delay Time
FSQ0170RNA
FSQ0270RNA
tf Fall Time
FSQ0170RNA
FSQ0270RNA
Control Section
fOSC
fOSC
DMAX
DMIN
VSTART
VSTOP
IFB
tS/S
Switching Frequency
Switching Frequency Variation(10)
Maximum Duty Cycle
Minimum Duty Cycle
UVLO Threshold Voltage
Feedback Source Current
Internal Soft-Start Time(10)
Condition
VDS = 700V, VGS = 0V
VDS = 560V, VGS = 0V,
TC = 125C
VGS = 10V, ID = 0.5A
VGS = 0V, VDS = 25V,
f = 1MHz
VDS = 350V, ID = 1.0A
-25C TA 85C
Measured at 0.1 x VDS
VFB = GND
VFB = GND
VFB = GND
VFB = 4V
Min. Typ. Max. Unit
50
A
200
8.8 11
6.0 7.2
250
550
25
pF
38
10
17
12
20
4
15
ns
30
55
10
25
92 100 108 KHz
±5 ±10 %
55 60 65 %
0 0 0%
11 12 13
789
V
0.7 0.9 1.1 mA
10 ms
© 2006 Fairchild Semiconductor Corporation
FSQ0170RNA, FSQ0270RNA Rev. 1.0.5
5
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Electrical Characteristics (Continued)
TA = 25C unless otherwise specified.
Symbol
Parameter
Condition
Burst-Mode Section
VBURH
VBURL Burst-Mode Voltage
VBUR(HYS)
Protection Section
FSQ0170RNA
ILIM Peak Current Limit FSQ0270RNA
tCLD
TSD
Current Limit Delay Time(10)
Thermal Shutdown Temperature(10)
VSD Shutdown Feedback Voltage
VOVP
Over-Voltage Protection
IDELAY
tLEB
Shutdown Delay Current
Leading Edge Blanking Time(10)
Total Device Section
IOP
Operating Supply Current
(Control Part Only)
ICH
VSTR
Startup Charging Current
Vstr Supply Voltage
TJ 25C
di/dt = 170mA/µs
di/dt = 200mA/µs
VFB = 4V
VCC = 14V
VCC = 0V,
RSTR<100k(12)
VCC = 0V
Notes:
10. These parameters, although guaranteed, are not 100% tested in production.
11. Pulse test: Pulse width 300µs, duty 2%.
12. RSTR is connected between the rectified AC line voltage source and VSTR pin.
Min. Typ. Max. Unit
0.5 0.6 0.7
V
0.3 0.4 0.5
V
100 200 300 mV
0.70 0.80 0.90
0.79 0.90 1.01
500
125 140
5.5 6.0 6.5
18 19
3.5 5.0 6.5
200
A
ns
C
V
V
A
ns
1 3 5 mA
0.70 0.85 1.00
24
mA
V
© 2006 Fairchild Semiconductor Corporation
FSQ0170RNA, FSQ0270RNA Rev. 1.0.5
6
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Typical Performance Characteristics (Control Part)
These characteristic graphs are normalized at TA= 25°C.
1.2
1.0
0.8
0.6
0.4
0.2
0.0
-25 0 25 50 75 100 125 150
Temperature [°C]
Figure 4. Operating Frequency (fOSC) vs. TA
1.2
1.0
0.8
0.6
0.4
0.2
0.0
-25
0
25 50 75 100 125 150
Temperature [°C]
Figure 5. Over-Voltage Protection (VOVP) vs. TA
1.2
1.0
0.8
0.6
0.4
0.2
0.0
-25 0 25 50 75 100 125 150
Temperature [°C]
Figure 6. Maximum Duty Cycle (DMAX) vs. TA
1.2
1.0
0.8
0.6
0.4
0.2
0.0
-25
0
25 50 75 100 125 150
Temperature [°C]
Figure 7. Operating Supply Current (IOP) vs. TA
1.2
1.0
0.8
0.6
0.4
0.2
0.0
-25 0 25 50 75 100 125 150
Temperature [°C]
1.2
1.0
0.8
0.6
0.4
0.2
0.0
-25
0
25 50 75 100 125 150
Temperature [°C]
Figure 8. Start Threshold Voltage (VSTART) vs. TA
Figure 9. Stop Threshold Voltage (VSTOP) vs. TA
© 2006 Fairchild Semiconductor Corporation
FSQ0170RNA, FSQ0270RNA Rev. 1.0.5
7
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Typical Performance Characteristics (Continued)
These characteristic graphs are normalized at TA= 25°C.
1.2
1.0
0.8
0.6
0.4
0.2
0.0
-25 0 25 50 75 100 125 150
Temperature [°C]
Figure 10. Feedback Source Current (IFB) vs. TA
1.2
1.0
0.8
0.6
0.4
0.2
0.0
-25
0
25 50 75 100 125 150
Temperature [°C]
Figure 11. Startup Charging Current (ICH) vs. TA
1.2
1.0
0.8
0.6
0.4
0.2
0.0
-25 0 25 50 75 100 125 150
Temperature [°C]
Figure 12. Peak Current Limit (ILIM) vs. TA
© 2006 Fairchild Semiconductor Corporation
FSQ0170RNA, FSQ0270RNA Rev. 1.0.5
8
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Functional Description
1. Startup: In previous generations of Fairchild Power
Switches (FPS™), the Vstr pin required an external
resistor to the DC input voltage line. In this generation,
the startup resistor is replaced by an internal high-
voltage current source and a switch that shuts off 10ms
after the supply voltage, VCC, goes above 12V. The
source turns back on if VCC drops below 8V.
VIN,dc
ISTR
Vstr
Vcc
Vcc<8V
UVLO on
J-FET
10ms after
Vcc12V
UVLO off
ICH
FSQ0x70RNA Rev. 1.00
Figure 13. High-Voltage Current Source
2. Feedback Control: The 700V FPS series employs
current-mode control, as shown in Figure 14. An opto-
coupler (such as the H11A817A) and shunt regulator
(such as the KA431) are typically used to implement the
feedback network. Comparing the feedback voltage with
the voltage across the Rsense resistor of SenseFET, plus
an offset voltage, makes it possible to control the
switching duty cycle. When the shunt regulator reference
pin voltage exceeds the internal reference voltage of
2.5V, the opto-coupler LED current increases, the
feedback voltage VFB is pulled down and thereby
reduces the duty cycle. This typically happens when the
input voltage increases or the output load decreases.
VO
431
VCC VCC
5A 900A
FB
3
CFB +
VFB
OSC
D1 D2
2.5R
VFB,in
-R
Gate
driver
FSQ0x70RNA Rev. 1.00 VSD
OLP
Figure 14. Pulse Width Modulation Circuit
3. Leading Edge Blanking (LEB): When the internal
SenseFET is turned on, the primary-side capacitance
and secondary-side rectifier diode reverse recovery
typically cause a high-current spike through the
SenseFET. Excessive voltage across the Rsense resistor
leads to incorrect feedback operation in the current-
mode PWM control. To counter this effect, the FPS
employs a Leading Edge Blanking (LEB) circuit. This
circuit inhibits the PWM comparator for a short time
(tLEB) after the Sense FET is turned on.
4. Protection Circuits: The FPS has several protective
functions, such as Overload Protection (OLP), Over-
Voltage Protection (OVP), Under-Voltage Lockout
(UVLO), and Thermal Shutdown (TSD). Because these
protection circuits are fully integrated in the IC without
external components, reliability is improved without
increasing cost. Once a fault condition occurs, switching
is terminated and the SenseFET remains off. This
causes VCC to fall. When VCC reaches the UVLO stop
voltage, VSTOP (typically 8V), the protection is reset and
the internal high-voltage current source charges the VCC
capacitor via the Vstr pin. When VCC reaches the UVLO
start voltage, VSTART (typically 12V), the FPS resumes
its normal operation. In this manner, the auto-restart can
alternately enable and disable the switching of the power
SenseFET until the fault condition is eliminated.
4.1 Overload Protection (OLP): Overload is defined as
the load current exceeding a pre-set level due to an
unexpected event. In this situation, the protection circuit
should be activated to protect the SMPS. However, even
when the SMPS is operating normally, the OLP circuit
can be activated during the load transition. To avoid this
undesired operation, the OLP circuit is designed to be
activated after a specified time to determine whether it is
a transient situation or a true overload situation. In
conjunction with the IPK current limit pin (if used), the
current mode feedback path limits the current in the
SenseFET when the maximum PWM duty cycle is
attained. If the output consumes more than this
maximum power, the output voltage (VO) decreases
below nominal voltage. This reduces the current through
the opto-coupler LED, which also reduces the opto-
coupler transistor current, thus increasing the feedback
voltage (VFB). If VFB exceeds 3V, the feedback input
diode is blocked and the 5µA current source (IDELAY)
starts to slowly charge CFB up to VCC. In this condition,
VFB increases until it reaches 6V, when the switching
operation is terminated, as shown in Figure 15. The
shutdown delay time is the time required to charge CFB
from 3V to 6V with 5µA current source.
VFB
FSQ0x70RNA Rev.00
Overload Protection
6V
3V
t12= CFB×(V(t2)-V(t1)) / IDELAY
t1
t12
CFB
V (t2 ) V (t1) ;
IDELAY
t2 t
IDELAY 5A, V (t1) 3V , V (t2 ) 6V
Figure 15. Overload Protection (OLP)
4.2 Thermal Shutdown (TSD): The SenseFET and the
control IC are integrated, making it easier for the control
© 2006 Fairchild Semiconductor Corporation
FSQ0170RNA, FSQ0270RNA Rev. 1.0.5
9
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IC to detect the temperature of the SenseFET. When the
temperature exceeds approximately 140C, thermal
shutdown is activated.
4.3 Over-Voltage Protection (OVP): In the event of a
malfunction in the secondary-side feedback circuit, or an
open feedback loop caused by a soldering defect, the
current through the opto-coupler transistor becomes
almost zero (see Figure 14). VFB climbs up in a similar
manner to the overload situation, forcing the preset
maximum current to be supplied to the SMPS until the
overload protection is activated. Because excess energy
is provided to the output, the output voltage may exceed
the rated voltage before the overload protection is
activated, resulting in the breakdown of the devices in
the secondary side. To prevent this situation, an Over-
Voltage Protection (OVP) circuit is employed. In general,
VCC is proportional to the output voltage and the FPS
uses VCC instead of directly monitoring the output
voltage. If VCC exceeds 19V, the OVP circuit is activated,
resulting in termination of the switching operation. To
avoid undesired activation of OVP during normal
operation, VCC should be designed to be below 19V.
5. Soft-Start: The FPS has an internal soft-start circuit
that slowly increases the SenseFET current after start-
up, as shown in Figure 16. The typical soft-start time is
10ms, where progressive increments of the SenseFET
current are allowed during the start-up phase. The pulse
width to the power switching device is progressively
increased to establish the correct working conditions for
transformers, inductors, and capacitors. The voltage on
the output capacitors is progressively increased to
smoothly establish the required output voltage. This also
helps prevent transformer saturation and reduces the
stress on the secondary diode during startup.
5V #6,7,8
DRAIN
ILIM Rsense
#1
GND
FSQ0x70RNA Rev. 1.00
Figure 16. Soft-Start Function
6. Burst Operation: To minimize power dissipation in
standby mode, the FPS enters burst-mode operation.
Feedback voltage decreases as the load decreases, as
shown in Figure 17, and the device automatically enters
burst-mode when the feedback voltage drops below
VBURH (typically 600mV). Switching continues until the
feedback voltage drops below VBURL (typically 400mV).
At this point, switching stops and the output voltage
starts to drop at a rate dependent on the standby current
load. This causes the feedback voltage to rise. Once it
passes VBURH, switching resumes. The feedback
voltage then falls and the process is repeated. Burst-
mode operation alternately enables and disables
switching of the SenseFET and reduces switching loss in
standby mode.
Burst Operation
Burst Operation
VFB Normal
Operation
VBURH
VBURL
Current
Waveform
Switching OFF
Switching
OFF
FSQ0x70RNA Rev.00
Figure 17. Burst Operation Function
7. Adjusting Peak Current Limit: As shown in Figure
18, a combined 2.8kinternal resistance is connected to
the non-inverting lead on the PWM comparator. An
external resistance of Rx on the current limit pin forms a
parallel resistance with the 2.8kwhen the internal
diodes are biased by the main current source of 900µA.
VCC
VFB IDELAY
3
5A
VCC
900A
IFB
2kΩ
PWM
Comparator
IPK
4
Rx
0.8kΩ
SenseFET
Current
Sense
FSQ0x70RNA Rev. 1.00
Figure 18. Peak Current Limit Adjustment
For example, FSQ0270RNA has a typical SenseFET
peak current limit (ILIM) of 0.9A. ILIM can be adjusted to
0.6A by inserting Rx between the IPK pin and the ground.
The value of the Rx can be estimated by the following
equations:
0.9A: 0.6A = 2.8k: Xk,
X = Rx || 2.8k
where X represents the resistance of the parallel network.
© 2006 Fairchild Semiconductor Corporation
FSQ0170RNA, FSQ0270RNA Rev. 1.0.5
10
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Application Information
Methods of Reducing Audible Noise
Switching-mode power converters have electronic and
magnetic components, which generate audible noise
when the operating frequency is in the range of
20~20,000Hz. Even though they operate above 20KHz,
they can make noise, depending on the load condition.
The following sections discuss methods to reduce noise.
Glue or Varnish
The most common method of reducing noise involves
using glue or varnish to tighten magnetic components.
The motion of core, bobbin, and coil and the chattering
or magnetostriction of core can cause the transformer to
produce audible noise. The use of rigid glue and varnish
helps reduce the transformer noise. Glue or varnish can
also can crack the core because sudden changes in the
ambient temperature cause the core and the glue to
expand or shrink in a different ratio.
Figure 19. Equal Loudness Curves
Ceramic Capacitor
Using a film capacitor instead of a ceramic capacitor as a
snubber capacitor is another noise reduction solution.
Some dielectric materials show a piezoelectric effect,
depending on the electric field intensity. Hence, a
snubber capacitor becomes one of the most significant
sources of audible noise. Another possibility is to use a
Zener clamp circuit instead of an RCD snubber for
higher efficiency as well as lower audible noise.
Adjusting Sound Frequency
Moving the fundamental frequency of noise out of the
2~4kHz range is the third method. Generally, humans
are more sensitive to noise in the range of 2~4kHz.
When the fundamental frequency of noise is located in
this range, the noise sounds louder although the noise
intensity level is identical (see Figure 19).
When the FPS acts in burst mode and the burst
operation is suspected to be a source of noise, this
method may be helpful. If the frequency of burst mode
operation lies in the range of 2~4kHz, adjusting the
feedback loop can shift the burst operation frequency. To
reduce the burst operation frequency, increase a
feedback gain capacitor (CF), opto-coupler supply
resistor (RD); and feedback capacitor (CB), and decrease
a feedback gain resistor (RF), as shown in Figure 20.
Figure 20. Typical Feedback Network of FPS
Other Reference Materials
AN-4134: Design Guidelines for Off-line Forward
Converters Using Fairchild Power Switch (FPS™)
AN-4137: Design Guidelines for Off-line Flyback
Converters Using Fairchild Power Switch (FPS™)
AN-4140: Transformer Design Consideration for Off-line
Flyback Converters using Fairchild Power Switch (FPS™)
AN-4141: Troubleshooting and Design Tips for Fairchild
Power Switch (FPS™) Flyback Applications
AN-4147: Design Guidelines for RCD Snubber of
Flyback
AN-4148: Audible Noise Reduction Techniques for
FPS™ Applications
© 2006 Fairchild Semiconductor Corporation
FSQ0170RNA, FSQ0270RNA Rev. 1.0.5
11
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Typical Application Circuit
Application
PC Auxiliary Power Supply
(Using FSQ0270RNA)
Output power
15W
Input Voltage
Universal input
(85-265 VAC)
Output Voltage (Max. Current)
5V (3A)
Features
High efficiency (> 78% at 115 VAC and 230 VAC input)
Low standby mode power consumption (< 0.8W at 230 VAC input and 0.5W load)
Enhanced system reliability through various protection functions
Internal soft-start (10ms)
Line UVLO function can be achieved using external component
Key Design Notes
The delay time for overload protection is designed to be about 30ms with C8 of 47nF. If faster/slower triggering of
OLP is required, C8 can be changed to a smaller/larger value (e.g. 100nF for about 60ms).
ZP1, DL1, RL1, RL2, RL3, RL4, RL5, RL7, QL1, QL2, and CL9 build a Line Under-Voltage Lockout block (UVLO).
The Zener voltage of ZP1 determines the input voltage that makes FPS turn on. RL5 and DL1 provide a reference
voltage from VCC. If the input voltage divided by RL1, RL2, and RL4 is lower than the Zener voltage of DL1, QL1 and
QL2 turn on and pull down VFB to ground.
An evaluation board and corresponding test report can be provided.
1. Schematic
C1
2.2nF
AC250V
RS1 CS1
9 1.5nF
L1
330H
CON1
1
R6
2.4 1W
2
3
Input
D2 D3
1N4007 1N4007
R2
4.7k
C2
22F
400V
D4 D5
1N4007 1N4007
R8
open
C3
22F
400V
C10
1nF
250V
ZP1
1N4762
ZDS1
P6KE180A
R14
30
DS1
1N4007
T1
EE2229
1 6,7
D1
SB540
3 9, 10
C4
1000F
16V
R3 R4
560 100
C9
1000F
16V
1
U1A
FOD817A
2
L2
1H
J4
0
R5
1.25k
1%
CON2
1
2
Output
C5
470F
10V
L3
0
J1
FB
RL1 1M
DL1 RL5
RL2 1N5233B 30k
1M
U3
FSQ0270RNA
8765
D6 R10
1N4007 2
4
5
3
U2
TL431A
2
C6
47nF
1
R9
10k
R11
1.2k
1%
QL1
KSP2907A
J3
open
RL4
120k
RL3
1k
J2
0
4
CL9
10F
50V
RL7 3
40k
QL2 U1B
KSP2222A FOD817A
1234
ZD2 C8
open 47nF
R13
open
ZR1 C7
80
47F
25V
R12
open
ZD1
1N4745
FSQ0x70RNA Rev. 1.12
Figure 21. Demo Circuit
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2. Transformer
EE2229
1 9, 10
Np/2 2
Np/2 3
6, 7 N5V
Na 4
5
FSQ0x70RNA Rev. 1.00
Figure 22. Transformer Schematic Diagram
3. Winding Specification
Pin (S F)
Np/2
3 2
Insulation: Polyester Tape t = 0.025mm, 1 Layers
Na 4 5
Insulation: Polyester Tape t = 0.025mm, 2 Layers
N5V 6, 7 9, 10
Insulation: Polyester Tape t = 0.025mm, 2 Layers
Np/2
2 1
Insulation: Polyester Tape t = 0.025mm, 2 Layers
Wire
0.31
0.252
0.652
0.31
Turns
72
22
8
72
Winding Method
Solenoid winding
Solenoid winding
Solenoid winding
Solenoid winding
4. Electrical Characteristics
Inductance
Leakage
Pin
1–3
1–3
Specification
1.20mH ± 5%
< 30µH Max
Remark
100kHz, 1V
Short all other pins
5. Core & Bobbin
Core: EE2229 (Material: PL-7, Ae = 35.7 mm2)
Bobbin: BE2229
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6. Demo Circuit Part List
Part Number
C6, C8
C1
C10
CS1
C2, C3
C4, C9
C5
C7
CL9
L1
L2
R6
J1, J2, J4, L3
R2
R3
R4
R5
R11
R9
R10
R14
RL3
RL1, RL2
RL4
RL5
RL7
RS1
ZR1
U1
U2
U3
QL1
QL2
D2, D3, D4, D5, D6, DS1
D1
ZD1
DL1
ZP1
ZDS1
Value
47nF
2.2nF (1KV)
1nF (200V)
1.5nF (50V)
22µF (400V)
1000µF (16V)
470µF (10V)
47µF (25V)
10µF (50V)
330µH
1µH
2.4 (1W)
0
4.7k
560
100
1.25k
1.2k
10k
2
30
1k
1M
120k
30k
40k
9
80
FOD817A
TL431
FSQ0270RNA
2N2907
2N2222
1N4007
SB540
1N4745
1N5233
82V (1W)
P6KE180A
Quantity
2
1
1
1
2
2
1
1
1
1
1
1
4
1
1
1
1
1
1
1
1
1
2
1
1
1
1
1
1
1
1
1
1
6
1
1
1
1
1
Description (Manufacturer)
Ceramic Capacitor
AC Ceramic Capacitor(X1 & Y1)
Mylar Capacitor
Ceramic Capacitor
Low Impedance Electrolytic Capacitor KMX series
Low ESR Electrolytic Capacitor NXC series
Low ESR Electrolytic Capacitor NXC series
General Electrolytic Capacitor
General Electrolytic Capacitor
Inductor
Inductor
Fusible Resistor
Jumper
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
IC (Fairchild Semiconductor)
IC (Fairchild Semiconductor)
IC (Fairchild Semiconductor)
IC (Fairchild Semiconductor)
IC (Fairchild Semiconductor)
Diode (Fairchild Semiconductor)
Schottky Diode (Fairchild Semiconductor)
Zener Diode (Fairchild Semiconductor)
Zener Diode (Fairchild Semiconductor)
Zener Diode (Fairchild Semiconductor)
TVS (Fairchild Semiconductor)
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7. Layout
Figure 23. Top Image of PCB
Figure 24. Bottom Image of PCB
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Package Dimensions
A
(.092) [Ø2.337]
PIN #1
[ ].400 10.15
.373 9.46
.036 [0.9 TYP]
.250±.005 [6.35±0.13]
(.032) [R0.813]
PIN #1
TOP VIEW
OPTION 1
7° TYP
B
[ ].070 1.78
.045 1.14
.310±.010 [7.87±0.25]
.130±.005 [3.3±0.13]
.210 MAX
[5.33]
7° TYP
TOP VIEW
OPTION 2
C
[ ].021 0.53
.015 0.37
.001[.025]
C
.015 MIN
[0.38]
[ ].140 3.55
.125 3.17
.100
[2.54]
NOTES:
A. CONFORMS TO JEDEC REGISTRATION MS-001,
VARIATIONS BA
B. CONTROLING DIMENSIONS ARE IN INCHES
REFERENCE DIMENSIONS ARE IN MILLIMETERS
C. DOES NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED
.010 INCHES OR 0.25MM.
D. DOES NOT INCLUDE DAMBAR PROTRUSIONS.
DAMBAR PROTRUSIONS SHALL NOT EXCEED
.010 INCHES OR 0.25MM.
E. DIMENSIONING AND TOLERANCING
PER ASME Y14.5M-1994.
.300
[7.62]
.430 MAX
[10.92]
.060 MAX
[1.52]
[ ].010+-..000005 0.254+-00..010207
N08EREVG
Figure 25. 8-Lead Dual In-Line Package (DIP)
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in
any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor
representative to verify or obtain the most recent revision. Package specifications do not expand the terms of
Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
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