E0C6266 Datasheet PDF
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PF428-10
E0C6266
4-bit Single Chip Microcomputer
WOPidpreeorVdauoticlotatnsge
q Core CPU Architecture
q 38.4kHz/500kHz Twin Clock Operation
q Built-in, 2-ch. Serial Ports
q SVD Circuit/2-ch. Analog Comparators
s DESCRIPTION
The E0C6266 is an advanced single-chip CMOS 4-bit microcomputer consisting of the E0C6200 CMOS 4-bit
core CPU. It also contains the ROM, RAM, 2-channel timer, event counter, start-stop serial ports, clock sync
serial ports and 40 I/O ports.
The E0C6266 provides an excellent solution for low-power consumption systems with clock functions.
s FEATURES
q CMOS LSI 4-bit parallel processing
q Clock ..................................................... 38.4kHz (Typ.)/500kHz (Max.) (selectable by software)
q Instruction set ........................................ 108 instructions
q Instruction cycle time ............................ 130µsec, 182µsec or 312µsec at 38kHz
(depending on instruction)
10µsec, 14µsec or 24µsec at 500kHz
(depending on instruction)
q ROM capacity ....................................... 6,144 × 12 bits
q RAM capacity ........................................ 1,024 × 4 bits
q Input port ............................................... 12 bits
q Output port ............................................ 16 bits
q I/O port .................................................. 12 bits
q Serial I/O port ........................................ 2 ports
Async; half-duplex, start-stop; transmission speed at 200, 300, 600, 1200, 2400 or 4800 bps;
6 to 8-bit data length; built-in error detect circuit and built-in send/receive buffer register.
Clock sync.; operating by external clock; start-stop can be set by mask option.
q Built-in time base counter, programmable timer, event counter, and watchdog timer
q Built-in SVD circuit, 2 channels (internal voltage detection)
q Built-in comparator, 2 channels
q Built-in LCD drive power supply, double boosting, external adjustment of output voltage
q Interrupts ............................................... External : Input interrupt
Internal : Timer interrupt
Comparator interrupt
Event counter interrupt
Serial I/O interrupt
3 lines
2 lines (4ch.)
2 lines
1 line
2 lines
q Supply voltage ...................................... 2.2V to 5.5V
q Current consumption ............................ HALT mode (38.4kHz)
: 1.8µA (Typ.)
OPERATING mode (500kHz) : 110µA (Typ.)/150µA (Max.)
q Package ................................................ QFP6-60pin (plastic)
Die form
SEIKO EPSON CORPORATION
1


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E0C6266
s BLOCK DIAGRAM
ROM
6,144 words x 12 bits
OSC
System Reset
Control
Core CPU E0C6200
K20~21
R30~31
K22~23
R32~33
VDD
VL1~4
CA~CE
VADJ
VS1
VSS
VSS2
P10~13
K10
RAM
1,024 words x 4 bits
Serial Port 1
Serial Port 2
Power
Controller
AMP & SVD
Interrupt
Generator
Input Port
Test Port
I/O Port
Output Port
Time Base
Counter
Programmable
Timer
Event
Counter
K00~03, K10~13, K20~23
TEST
P00~03, P10~13, P20~23
R00~03, R10~13, R20~23, R30~33
K13
2


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E0C6266
s PIN CONFIGURATION
QFP6-60pin
45
46
31
30
E0C6266
INDEX
60 16
1 15
No. Pin name No. Pin name No. Pin name No. Pin name
1 P13
16 VSS2
31 K20
46 VL1
2 P20
17 R22
32 K21
47 VDD
3 P21
18 R23
33 K22
48 OSC1
4 P22
19 R30
34 K23
49 OSC2
5 P23
20 R31
35 RESET 50 VS1
6 R00
21 R32
36 TEST
51 OSC3
7 R01
22 R33
37 CE
52 OSC4
8 R02
23 K00
38 CD
53 VSS
9 R03
24 K01
39 CC
54 P00
10 R10
25 K02
40 CB
55 P01
11 R11
26 K03
41 CA
56 P02
12 R12
27 K10
42 VL4
57 P03
13 R13
28 K11
43 VL3
58 P10
14 R20
29 K12
44 VL2
59 P11
15 R21
30 K13
45 VADJ
60 P12
s PIN DESCRIPTION
Pin name
VDD
VSS
VSS2
VS1
VL1
VL2
VL3
VL4
VADJ
CA–CE
OSC1
OSC2
OSC3
OSC4
RESET
K00–K03
K10/VBLD
K11–K12
K13/EVN
K20/SI1A
K21/SI1B
K22/SI2
K23/SCLK
P00–P03
P10/CMPP1
P11/CMPM1
P12/CMPP2
P13/CMPM2
P20–P23
R00–R03
R10, R11
R12/FOUT
R13/BZ
R20–R23
R30/SO1A
R31/SO1B
R32/SO2
R33/SRDY
TEST
Pin No.
47
53
16
50
46
44
43
42
45
41–37
48
49
51
52
35
23–26
27
28–29
30
31
32
33
34
54–57
58
59
60
1
2–5
6–9
10, 11
12
13
14, 15, 17, 18
19
20
21
22
36
In/Out
I
I
I
I
I
O
I
O
I
I
I
I
I
I
I
I
I
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O
O
O
O
O
O
I
Function
Power source (+) terminal
Power source (-) terminal ...analog power source
Power source (-) terminal ...power source for output ports (R20–R23)
Power source for oscillation circuit
Reduction power source for LCD
Power source for LCD
Booster power source for LCD
Booster power source for LCD
Input terminal for setting VL
Booster/reduction capacitor connecting terminals for LCD
Crystal oscillation input terminal
Crystal oscillation output terminal
Ceramic oscillation input terminal
Ceramic oscillation output terminal
Initial reset input terminal
Input terminal
Input terminal (Input terminal for setting SVD detection voltage)
Input terminal
Input terminal (Event counter input terminal)
Input terminal (Serial port 1 data input terminal)
Input terminal (Serial port 1 data input terminal)
Input terminal (Serial port 2 data input terminal)
Input terminal (Serial port 2 clock input terminal)
I/O terminal
I/O terminal
(Comparator 1 non-inverted input terminal)
I/O terminal
(Comparator 1 inverted input terminal)
I/O terminal
(Comparator 2 non-inverted input terminal)
I/O terminal
(Comparator 2 inverted input terminal)
I/O terminal
Output terminal
Output terminal
Output terminal (FOUT or BZ output terminal)
Output terminal (BZ or OSC3 clock output terminal)
Output terminal (10 mA output available)
Output terminal (Serial port 1 data output terminal)
Output terminal (Serial port 1 data output terminal)
Output terminal (Serial port 2 data output terminal)
Output terminal (Serial port 2 status output terminal)
Test input terminal
3


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E0C6266
s ELECTRICAL CHARACTERISTICS
q Absolute Maximum Ratings
(VDD=0V)
Rating
Symbol
Value
Unit
Supply voltage (1)
VSS
-7.0 to 0.5
V
Supply voltage (2)
VSS2
-7.0 to VSS
V
Supply voltage (3)
VL1–VL4
-7.0 to 0.5
V
Input voltage (1)
VI
VSS - 0.3 to 0.3
V
Input voltage (2) *1
VIOSC
-2.0 to 0.3
V
Permissible total output current (1)*2 ΣIVSS 15 mA
Permissible total output current (2)*2 ΣIVSS2
40
mA
Operating temperature
Topr
-20 to 70
°C
Storage temperature
Tstg
-65 to 150
°C
Soldering temperature / Time
Tsol
260°C, 10sec (lead section)
Permissible dissipation *3
PD
250 mW
1: OSC1, OSC2 pin
2: The permissible total output current is the sum total of the current (average current) that simultaneously flows from the output pins (or is draw in).
3: In case of plastic package (QFP6-60pin).
q Recommended Operating Conditions
(Ta=-20 to 70°C)
Condition
Symbol
Remark
Min.
Typ.
Max.
Unit
Supply voltage (1)
VSS VDD=0V
-5.5 -2.2 V
Supply voltage (2) *1
VSS2 VDD=0V
-5.5 VSS V
Oscillation frequency (1)
fOSC1
– 38.400 –
kHz
Oscillation frequency (2) *2
fOSC3 duty: 50±5%
50 500 kHz
Capacitor between VDD and VS1 CS1
0.1 µF
Capacitor between VDD and VL1 *3 CL1
0.1 µF
Capacitor between VDD and VL2 *3 CL2
0.1 µF
Capacitor between VDD and VL3 *3 CL3
0.1 µF
Capacitor between VDD and VL4 *3 CL4
0.1 µF
Capacitor between CA and CB *3 C1
0.1 µF
Capacitor between CA and CC *3 C2
0.1 µF
Capacitor between CD and CE *3 C3
0.1 µF
1: When selecting not to use VSS2 power by option, you can release the VSS2 terminal.
2: When selecting not to use OSC3 oscillation circuit by option, you can release the OSC3 terminal.
3: When selecting not to use LCD drive power by option, you can release the above capacitors are not required. However, you should
connect VL1–VL4 terminals with the VDD and release the CA–CE and VADJ terminals.
q DC Characteristics
Characteristic
High level input voltage (1)
Symbol
VIH1
High level input voltage (2)
Low level input voltage (1)
VIH2
VIL1
Low level input voltage (2)
High level input current
VIL2
IIH
VIH=VDD
Low level input current (1) IIL1 VIL1=VSS
No pull up resistor
Low level input current (2) IIL2 VIL2=VSS
With pull up resistor
Low level input current (3) IIL3 VIL3=VSS
With pull up resistor
Low level input current (4) IIL4 VIL4=VSS
Low level input current (5) IIL5 VIL5=0.1•VSS
High level output current (1) IOH1 VOH1=0.1•VSS
High level output current (2) IOH2 VOH2=0.1•VSS2
Low level output current (1) IOL1 VOL1=0.9•VSS
Low level output current (2) IOL2 VOL2=0.9•VSS2
(Unless otherwise specified: VDD=0V, VSS(VSS2)=-2.2 to -5.5V, Ta=25°C)
Condition
Min.
Typ.
Max.
Unit
K00–03•10–13•20–23
0.2•VSS
0V
P00–03•10–13•20–23
RESET
0.1•VSS
0V
K00–03•10–13•20–23
VSS
0.8•VSS
V
P00–03•10–13•20–23
RESET
VSS
0.9•VSS
V
K00–03•10–13•20–23
0.5 µA
P00–03•10–13•20–23
RESET, TEST
K00–03•10–13•20–23
-0.5
µA
P00–03•10–13•20–23
K00–03•10–13•20–23
-20
-3 µA
P00–03•10–13•20–23
-30
-3 µA
RESET
RESET
R00–03•10–13•30–33•40–43
P00–03•10–13•20–23
R20–23
R00–03•10–13•30–33•40–43
P00–03•10–13•20–23
R20–23
-20
-100
500
5
-0.5
-300
-300
µA
µA
µA
µA
µA
mA
4


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E0C6266
q Analog Circuit Characteristics and Current Consumption
(Unless otherwise specified: VDD=0V, VSS=-2.2 to -5.5V, fOSC1=38.4kHz(crystal), fOSC3=500kHz(ceramic),
Ta=25°C, CG=10pF, CGC/CDC=108pF, VADJ=VL2, RA1/RA2=1M, CS1/CL1–CL4/C1–C3=0.1µF)
Characteristic
Symbol
Condition
Min.
Typ.
Max.
Unit
LCD drive voltage *1
VL1 Connect 1Mload resistor between VDD and VL1
0.50
0.45 V
(No panel load), VSS=-2.5 to -5.5V
×VL2
×VL2
VL2 Connect 1Mload resistor between VDD and VL2
-2.25
-2.10
-1.95
V
(No panel load), VSS=-2.5 to -5.5V
VL3 Connect 1Mload resistor between VDD and VL3
1.50
1.45 V
(No panel load), VSS=-2.5 to -5.5V
×VL2
×VL2
VL4 Connect 1Mload resistor between VDD and VL4
2.00
1.95 V
(No panel load), VSS=-2.5 to -5.5V
×VL2
×VL2
BLD voltage (internal)
VBLD1
-2.50
-2.35
-2.20
V
BLD voltage (external)
VBLD2
-1.13
-1.05
-0.97
V
BLD circuit stability time *2 tBLD
100 µS
BLD circuit current
IBLD VSS=-3.0V
10 20 µA
consumption
Analog comparator
VIP Noninverted input (CMPP)
VSS+0.3
-1.0 V
input voltage
VIM Inverted input (CMPM)
Analog comparator
VOF VIP=-1.0 to VSS+0.3V
50 mV
offset voltage
VIM=-1.0 to VSS+0.3V
Analog comparator
tCMP1 VIP=-1.0 to VSS+0.3V
100 µS
stabilizing time *2
VIM=-1.0 to VSS+0.3V
Analog comparator
tCMP2 VSS=-2.2V
100 µS
response time
VIP=-1.1V, VIM=-1.1±0.1V
Analog comparator
ICMP1 VSS=-3.0V
4 10 µA
current consumption (1)
VIP=-1.4V, VIM=-1.6V
Analog comparator
ICMP2 VSS=-3.0V
8 15 µA
current consumption (2)
VIP=-1.6V, VIM=-1.4V
Current consumption
IOP During HALT (1) *3
OSCC="0"
1.8 4.0 µA
During HALT (2) *4
No panel load
1.3 3.0 µA
During operation at 38.4kHz *3
9 15 µA
During operation at 500kHz *5 No panel load
110 150 µA
1: When selecting not to use LCD drive power by option, VDD (=0V) is output to VL2.
2: The stabilizing time is the time from turning the circuit on until the output data stabilizes.
3: The time base counter is RUN status, programmable timer, BLD circuit and analog comparator are OFF status, and the input and
output terminals are static status.
4: The same status as 1 and is when not using LCD drive power by option, and selecting DC output to the R12 port output form.
5: The BLD circuit and analog comparator are OFF status and the input and output terminals are static status.
q Oscillation Characteristics
The oscillation characteristics change depending on the conditions (components used, board pattern, etc.). Use the follow-
ing characteristics as reference values.
OSC1 crystal oscillation circuit
(Unless otherwise specified: VDD=0V, VSS=-2.2 to -5.5V, Crystal: C2-TYPE(Seiko Epson), CG=25pF, CD=built-in, Ta=25°C)
Characteristic
Oscillation start time
Symbol
Condition
tsta VSS=-2.2 to -5.5V
Min.
Typ.
Max.
Unit
3 Sec
Built-in capacitance (drain)
Frequency/voltage deviation
CD For 60 pin plastic package
f/V VSS=-2.2 to -5.5V
– 20 – pF
5 ppm
Frequency/IC deviation
Frequency adjustment range
Permitted leak resistance
f/IC
f/CG CG=5 to 25pF
Rleak Between OSC1 and VDD, VS1
-10 10 ppm
40 ppm
200 M
OSC3 ceramic oscillation circuit
(Unless otherwise specified: VDD=0V, VSS=-2.2 to -5.5V, Ceramic: CSB500E(Murata Mfg. Co.), CGC=CDC=108pF, Ta=25°C)
Characteristic
Symbol
Condition
Min.
Typ.
Max.
Unit
Oscillation start time
tsta VSS=-2.2 to -5.5V
4 10 mS
5


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E0C6266
s BASIC EXTERNAL CONNECTION DIAGRAM
RA1
CL1
C2
CL2 CL4
CL3 C1
RA2
C3
3.0V
CD
C GX
X'tal
CS1
C GC
CR
C DC
VDD
OSC1
OSC2
VS1
OSC3
OSC4
VSS
E0C6266
TEST
RESET
VSS2
CSR
SSR
X'tal Crystal oscillator 38.4kHz
CGX Trimmer capacitor 5~25pF
CR Ceramic oscillator 500kHz
CGC
108pF
CDC 108pF
CSR 3.3µF
RA1, RA2
1M
CL1~CL4
0.1µF
C1~C3
0.1µF
CS1 0.1µF
CD 6.8µF
Note: The above table is simply an example, and is not guaranteed to work.
s PACKAGE DIMENSIONS
Plastic QFP6-60pin
45
46
17.6±0.4
14±0.2
31
30
INDEX
60
16
1 15
0.8 0.35±0.1
0.15±0.05
0°
10°
0.85±0.2
1.8
Unit: mm
6


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E0C6266
NOTICE:
No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko
Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability of any kind arising out of
any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation that
this material is applicable to products requiring high level reliability, such as, medical products. Moreover, no license to any intellectual
property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accordance with this
material will be free from any patent or copyright infringement of a third party. This material or portions thereof may contain technology or the
subject relating to strategic products under the control of the Foreign Exchange and Foreign Trade Control Law of Japan and may require an
export license from the Ministry of International Trade and Industry or other approval from another government agency.
© Seiko Epson Corporation 1999 All right reserved.
SEIKO EPSON CORPORATION
ELECTRONIC DEVICES MARKETING DIVISION
IC Marketing & Engineering Group
ED International Marketing Department I (Europe & U.S.A.)
421-8, Hino, Hino-shi, Tokyo 191-8501, JAPAN
Phone : 042-587-5812 FAX : 042-587-5564
ED International Marketing Department II (Asia)
421-8, Hino, Hino-shi, Tokyo 191-8501, JAPAN
Phone : 042-587-5814 FAX : 042-587-5110





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